CHAPTER 1 OUTLINE
9
1.8 Outline of Function
Item
Internal
memory
Part Number
μ
PD78042F
μ
PD78043F
μ
PD78044F
μ
PD78045F
μ
PD78P048A
ROM
Mask ROM
One-time
PROM/EPROM
16 Kbytes
24 Kbytes
32 Kbytes
40 Kbytes
60 Kbytes
Note 1
High-speed RAM 512 bytes
1024 bytes
1024 bytes
1024 bytes
Note 2
Expansion RAM
—
1024 bytes
Note 3
Buffer RAM
64 bytes
FIP display RAM
48 bytes
General register
8 bits
×
8
×
4 banks
Minumum
instruction
execution
time
With main system
clock selected
0.4
μ
s/0.8
μ
s/1.6
μ
s/3.2
μ
s/6.4
μ
s
(when operated at 5.0 MHz)
With subsystem
clock selected
122
μ
s (when operated at 32.768 kHz)
Instruction set
16-bit operation
Multiply/divide (8-bit
×
8-bit, 16-bit / 8-bit)
Bit manipulate (set, reset, test, and Boolean operation)
BCD adjust, and other related operations
I/O port (Includes FIP dual-function pins)
Total
:
:
:
:
:
:
68 I/O pins
2 pins
27 pins
5 pins
16 pins
18 pins
CMOS input
CMOS input/output
N-ch open-drain I/O
P-ch open-drain I/O
P-ch open-drain output
FIP controller/driver
Total of display output
Segments
Digits
:
:
:
34 outputs
9 to 24 pins
2 to 16 pins
A/D converter
8-bit resolution
×
8 channels
Power supply voltage : AV
DD
= 4.0 to 5.5 V
Serial interface
3-wire serial I/O/SBI/2-wire serial I/O mode selection
possible
3-wire serial I/O mode (Maximum 64-byte on-chip automatic transmit/
receive function)
: 1 channel
: 1 channel
Timer
16-bit timer/event counter
8-bit timer/event counter
Watch timer
Watchdog timer
6-bit up/down counter
: 1 channel
: 2 channels
: 1 channel
: 1 channel
: 1 channel
Timer output
3 outputs: (14-bit PWM generation possible from one output)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz
(@ 5.0 MHz with main system clock)
32.768 kHz (@ 32.768 kHz with subsystem clock)
Notes 1.
16 K, 24 K, 32 K, 40 K or 60 Kbytes can be selected by the memory size switching register (IMS).
2.
512 or 1024 bytes can be selected by IMS.
3.
0 or 1024 bytes can be selected by the internal expansion RAM switching register (IXS).