5
μ
PD78052(A), 78053(A), 78054(A)
Memory space
General registers
Instruction cycle
When main system clock
selected
When subsystem clock
selected
Instruction set
I/O ports
A/D converter
D/A converter
Serial interface
Timer
Timer output
Clock output
Buzzer output
V
DD
= 2.0 to 6.0 V
T
A
= –40 to +85
°
C
80-pin plastic QFP (14
×
14 mm)
16 Kbytes
512 bytes
32 bytes
64 Kbytes
8 bits
×
32 registers (8 bits
×
8 registers
×
4 banks)
On-chip instruction execution time cycle modification function
24 Kbytes
1024 bytes
32 Kbytes
0.4
μ
s/0.8
μ
s/1.6
μ
s/3.2
μ
s/6.4
μ
s/12.8
μ
s (at 5.0-MHz operation)
122
μ
s (at 32.768-kHz operation)
16-bit operation
Multiplication/division (8 bits
×
8 bits,16 bits
÷
8 bits)
Bit manipulation (set, reset, test, boolean operation)
BCD adjustment, etc.
Total
CMOS input
CMOS I/O
N-ch open-drain I/O
8-bit resolution
×
8 channels
8-bit resolution
×
2 channels
3-wire serial I/O, SBI, or 2-wire serial I/O mode selectable: 1 channel
3-wire serial I/O mode (on-chip max. 32 bytes automatic transmit/receive
function): 1 channel
3-wire serial I/O or UART mode selectable: 1 channel
16-bit timer/event counter
: 1 channel
8-bit timer/event counter
: 2 channels
Watch timer
: 1 channel
Watchdog timer
: 1 channel
: 69
:
0
2
: 63
:
0
4
3 (14-bit PWM output
×
1)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz,
5.0 MHz (at main system clock 5.0-MHz operation)
32.768 kHz (at subsystem clock 32.768-kHz operation)
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 5.0-MHz operation)
Internal : 13, external : 7
Internal : 1
1
Internal : 1, external : 1
FUNCTION OVERVIEW
Part Number
Item
μ
PD78052(A)
μ
PD78053(A)
μ
PD78054(A)
Internal
memory
ROM
High-speed RAM
Buffer RAM
Vectored
interrupt
source
Maskable
Non-maskable
Software
Test input
Power supply voltage
Operating ambient temperature
Package