53
μ
PD78052(A), 78053(A), 78054(A)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK1 cycle time
t
KCY7
4.5 V
≤
V
DD
≤
6.0 V
800
ns
2.7 V
≤
V
DD
< 4.5 V
1600
ns
3200
ns
SCK1 high-/low-level
t
KH7
,
V
DD
= 4.5 to 6.0 V
t
KCY7
/2–50
ns
width
t
KL7
t
KCY7
/2–100
ns
SI1 setup time
t
SIK7
4.5 V
≤
V
DD
≤
6.0 V
100
ns
(to SCK1
↑
)
2.7 V
≤
V
DD
< 4.5 V
150
ns
300
ns
SI1 hold time
t
KSI7
400
ns
(from SCK1
↑
)
SO1 output delay time
t
KSO7
C = 100 pF
Note
300
ns
from SCK1
↓
(b) Serial interface channel 1
(i)
3-wire serial I/O mode (SCK1... Internal clock output)
Note
C is the load capacitance of the SO1 output line.
(ii) 3-wire serial I/O mode (SCK1... External clock input)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK1 cycle time
t
KCY8
4.5 V
≤
V
DD
≤
6.0 V
800
ns
2.7 V
≤
V
DD
< 4.5 V
1600
ns
3200
ns
SCK1 high-/low-level
t
KH8
,
4.5 V
≤
V
DD
≤
6.0 V
400
ns
width
t
KL8
2.7 V
≤
V
DD
< 4.5 V
800
ns
1600
ns
SI1 setup time
t
SIK8
100
ns
(to SCK1
↑
)
SI1 hold time
t
KSI8
400
ns
(from SCK1
↑
)
SO1 output delay
t
KSO8
C = 100 pF
Note
300
ns
time from SCK1
↓
SCK1 rise, fall time
t
R8
, t
F8
When using external device
expansion function
160
ns
When not using external
device expansion function
1000
ns
Note
C is the load capacitance of the SO1 output line.