參數(shù)資料
型號: μPD78054(A)
廠商: NEC Corp.
英文描述: 8 Bit Single Chip Microcontrollers(8位單片微控制器)
中文描述: 8位單片機微控制器(8位單片微控制器)
文件頁數(shù): 46/76頁
文件大?。?/td> 386K
代理商: ΜPD78054(A)
46
μ
PD78052(A), 78053(A), 78054(A)
Remarks
1.
2.
3.
4.
MCS: Oscillation mode selection register (OSMS) bit 0
PCC2 to PCC0: Processor clock control register (PCC) bit 2 to bit 0
t
CY
= T
CY
/4
n indicates the number of waits.
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASTB high-level width
t
ASTH
0.85t
CY
–50
ns
Address setup time
t
ADS
0.85t
CY
–50
ns
Address hold time
t
ADH
50
ns
Data input time from address
t
ADD1
(2.85+2n)t
CY
–80
ns
t
ADD2
(4+2n)t
CY
–100
ns
Data input time from RD
t
RDD1
(2+2n)t
CY
–100
ns
t
RDD2
(2.85+2n)t
CY
–100
ns
Read data hold time
t
RDH
0
ns
RD low-level width
t
RDL1
(2+2n)t
CY
–60
ns
t
RDL2
(2.85+2n)t
CY
–60
ns
WAIT
input time from RD
t
RDWT1
0.85t
CY
–50
ns
t
RDWT2
2t
CY
–60
ns
WAIT
input time from WR
t
WRWT
2t
CY
–60
ns
WAIT low-level width
t
WTL
(1.15+2n)t
CY
(2+2n)t
CY
ns
Write data setup time
t
WDS
(2.85+2n)t
CY
–100
ns
Write data hold time
t
WDH
20
ns
WR low-level width
t
WRL
(2.85+2n)t
CY
–60
ns
RD
delay time from ASTB
t
ASTRD
25
ns
WR
delay time from ASTB
t
ASTWR
0.85t
CY
+20
ns
ASTB
delay time from
RD
in external fetch
t
RDAST
0.85t
CY
–10
1.15t
CY
+20
ns
Address hold time from
RD
in external fetch
t
RDADH
0.85t
CY
–50
1.15t
CY
+50
ns
Write data output time from RD
t
RDWD
40
ns
Write data output time from WR
t
WRWD
0
50
ns
Address hold time from WR
t
WRADH
0.85t
CY
1.15t
CY
+40
ns
RD
delay time from WAIT
t
WTRD
1.15t
CY
+40
3.15t
CY
+40
ns
WR
delay time from WAIT
t
WTWR
1.15t
CY
+30
3.15t
CY
+30
ns
(2) READ/WRITE OPERATION
(a) When MCS = 1, PCC2 to PCC0 = 000B (T
A
= –40 to +85
°
C, V
DD
= 4.5 to 6.0 V)
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