參數(shù)資料
型號(hào): μPD78054(A)
廠商: NEC Corp.
英文描述: 8 Bit Single Chip Microcontrollers(8位單片微控制器)
中文描述: 8位單片機(jī)微控制器(8位單片微控制器)
文件頁(yè)數(shù): 47/76頁(yè)
文件大?。?/td> 386K
代理商: ΜPD78054(A)
47
μ
PD78052(A), 78053(A), 78054(A)
(b) Except when MCS = 1, PCC2 to PCC0 = 000B (T
A
= –40 to +85
°
C, V
DD
= 2.0 to 6.0 V) (1/2)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASTB high-level width
t
ASTH
V
DD
= 2.7 to 6.0 V
t
CY
–80
ns
t
CY
–150
ns
Address setup time
t
ADS
V
DD
= 2.7 to 6.0 V
t
CY
–80
ns
t
CY
–150
ns
Address hold time
t
ADH
V
DD
= 2.7 to 6.0 V
0.4t
CY
–10
ns
0.37t
CY
–40
ns
Data input time from address
t
ADD1
V
DD
= 2.7 to 6.0 V
(3+2n)t
CY
–160
ns
(3+2n)t
CY
–320
ns
t
ADD2
V
DD
= 2.7 to 6.0 V
(4+2n)t
CY
–200
ns
(4+2n)t
CY
–300
ns
Data input time from RD
t
RDD1
V
DD
= 2.7 to 6.0 V
(1.4+2n)t
CY
–70
ns
(1.37+2n)t
CY
–120
ns
t
RDD2
V
DD
= 2.7 to 6.0 V
(2.4+2n)t
CY
–70
ns
(2.37+2n)t
CY
–120
ns
Read data hold time
t
RDH
0
ns
RD low-level width
t
RDL1
V
DD
= 2.7 to 6.0 V
(1.4+2n)t
CY
–20
ns
(1.37+2n)t
CY
–20
ns
t
RDL2
V
DD
= 2.7 to 6.0 V
(2.4+2n)t
CY
–20
ns
(2.37+2n)t
CY
–20
ns
WAIT
input time from RD
t
RDWT1
V
DD
= 2.7 to 6.0 V
t
CY
–100
ns
t
CY
–200
ns
t
RDWT2
V
DD
= 2.7 to 6.0 V
2t
CY
–100
ns
2t
CY
–200
ns
WAIT
input time from WR
t
WRWT
V
DD
= 2.7 to 6.0 V
2t
CY
–100
ns
2t
CY
–200
ns
WAIT low-level width
t
WTL
(1+2n)t
CY
(2+2n)t
CY
ns
Write data setup time
t
WDS
V
DD
= 2.7 to 6.0 V
(2.4+2n)t
CY
–60
ns
(2.37+2n)t
CY
–100
ns
Write data hold time
t
WDH
20
ns
WR low-level width
t
WRL
V
DD
= 2.7 to 6.0 V
(2.4+2n)t
CY
–20
ns
(2.37+2n)t
CY
–20
ns
RD
delay time from ASTB
t
ASTRD
V
DD
= 2.7 to 6.0 V
0.4t
CY
–30
ns
0.37t
CY
–50
ns
WR
delay time from ASTB
t
ASTWR
V
DD
= 2.7 to 6.0 V
1.4t
CY
–30
ns
1.37t
CY
–50
ns
Remarks
1.
2.
3.
4.
MCS: Oscillation mode selection register (OSMS) bit 0
PCC2 to PCC0: Processor clock control register (PCC) bit 2 to bit 0
t
CY
= T
CY
/4
n indicates the number of waits.
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