22
LIST OF FIGURES (2/9)
Figure No.
Title
Page
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
Block Diagram of Clock Generator ............................................................................................ 166
Subsystem Clock Feedback Resistor ........................................................................................ 167
Processor Clock Control Register Format................................................................................. 168
Oscillation Mode Selection Register Format ............................................................................. 170
Main System Clock Waveform due to Writing to OSMS .......................................................... 170
External Circuit of Main System Clock Oscillator ..................................................................... 171
External Circuit of Subsystem Clock Oscillator......................................................................... 172
Examples of Oscillator with Bad Connection ............................................................................ 172
Main System Clock Stop Function............................................................................................. 176
System Clock and CPU Clock Switching .................................................................................. 179
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
16-Bit Timer/Event Counter Block Diagram .............................................................................. 186
16-Bit Timer/Event Counter Output Control Circuit Block Diagram ......................................... 187
Timer Clock Selection Register 0 Format ................................................................................. 191
16-Bit Timer Mode Control Register Format ............................................................................. 192
Capture/Compare Control Register 0 Format ........................................................................... 193
16-Bit Timer Output Control Register Format ........................................................................... 194
Port Mode Register 3 Format..................................................................................................... 195
External Interrupt Mode Register 0 Format............................................................................... 196
Sampling Clock Select Register Format.................................................................................... 197
Control Register Settings for Interval Timer Operation ............................................................ 198
Interval Timer Configuration Diagram........................................................................................ 199
Interval Timer Operation Timings .............................................................................................. 199
Control Register Settings for PWM Output Operation .............................................................. 201
Example of D/A Converter Configuration with PWM Output .................................................... 202
TV Tuner Application Circuit Example....................................................................................... 202
Control Register Settings for PPG Output Operation ............................................................... 203
Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register ......................................................................................................... 204
Configuration Diagram for Pulse Width Measurement by Free-Running Counter .................. 205
Timing of Pulse Width Measurement Operation by Free-Running Counter and
One Capture Register (with Both Edges Specified) ................................................................. 205
Control Register Settings for Two Pulse Width Measurements with
Free-Running Counter ................................................................................................................ 206
Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified) ....................................................................................................... 207
Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers............................................................................................................... 208
Timing of Pulse Width Measurement Operation by Free-Running Counter and
Two Capture Registers (with Rising Edge Specified)............................................................... 209
Control Register Settings for Pulse Width Measurement by Means of Restart ...................... 210
Timing of Pulse Width Measurement Operation by Means of Restart
(with Rising Edge Specified) ...................................................................................................... 210
8-18
8-19
8-20
8-21
8-22
8-23
8-24
8-25