– vi –
FIGURE (1/4)
Fig. No.
Title
Page
2-1
Pin Input/Output Circuit of List............................................................................................
23
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
Memory Map (
μ
PD78081) ..................................................................................................
Memory Map (
μ
PD78082) ..................................................................................................
Memory Map (
μ
PD78P083)................................................................................................
Data Memory Addressing (
μ
PD78081)...............................................................................
Data Memory Addressing (
μ
PD78082)...............................................................................
Data Memory Addressing (
μ
PD78P083) ............................................................................
Program Counter Configuration .........................................................................................
Program Status Word Configuration...................................................................................
Stack Pointer Configuration................................................................................................
Data to be Saved to Stack Memory....................................................................................
Data to be Reset from Stack Memory ................................................................................
General Register Configuration ..........................................................................................
25
26
27
30
31
32
33
33
35
35
35
36
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
Port Types ..........................................................................................................................
P00 Block Diagram.............................................................................................................
P01 to P03 Block Diagram .................................................................................................
P10 to P17 Block Diagram .................................................................................................
P30 to P37 Block Diagram .................................................................................................
P50 to P57 Block Diagram .................................................................................................
P70 Block Diagram.............................................................................................................
P71 and P72 Block Diagram ..............................................................................................
P100 to P101 Block Diagram .............................................................................................
Port Mode Register Format ................................................................................................
Pull-Up Resistor Option Register Format ...........................................................................
53
56
56
57
58
59
60
61
62
65
66
5-1
5-2
5-3
5-4
5-5
5-6
5-7
Block Diagram of Clock Generator .....................................................................................
Processor Clock Control Register Format ..........................................................................
Oscillation Mode Selection Register Format ......................................................................
Main System Clock Waveform due to Writing to OSMS.....................................................
External Circuit of Main System Clock Oscillator ...............................................................
Examples of Oscillator with Bad Connection (1/2) .............................................................
CPU Clock Switching .........................................................................................................
70
71
72
73
74
78
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
8-Bit Timer/Event Counters 5 and 6 Block Diagram ...........................................................
Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit ...................
Timer Clock Select Register 5 Format................................................................................
Timer Clock Select Register 6 Format................................................................................
8-Bit Timer Mode Control Register 5 Format......................................................................
8-Bit Timer Mode Control Register 6 Format......................................................................
Port Mode Register 10 Format ...........................................................................................
8-Bit Timer Mode Control Register Settings for Interval Timer Operation ..........................
Interval Timer Operation Timings .......................................................................................
82
83
85
86
87
88
89
90
91