參數(shù)資料
型號: μPD78F0034Y
廠商: NEC Corp.
元件分類: 8位微控制器
英文描述: 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
中文描述: 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存
文件頁數(shù): 31/52頁
文件大?。?/td> 309K
代理商: ΜPD78F0034Y
m
PD78F0034Y
Preliminary Data Sheet
31
(f)
I
2
C bus Mode
Standard Mode
High-speed Mode
Unit
Parameter
Symbol
MIN.
MAX.
MIN.
MAX.
SCL0 clock frequency
f
CLK
0
100
0
400
kHz
Bus free time
(between stop and start conditions)
t
BUF
4.7
1.3
m
s
Hold time
Note 1
t
HD:STA
4.0
0.6
m
s
SCL0 clock low-level width
t
LOW
4.7
1.3
m
s
SCL0 clock high-level width
t
HIGH
4.0
0.6
m
s
Start/restart condition setup time
t
SU:STA
4.7
0.6
m
s
Data hold time
CBUS compatible master
t
HD:DAT
5.0
m
s
I
2
C bus
0
Note 2
0
Note 2
0.9
Note 3
m
s
Data setup time
t
SU:DAT
250
100
Note 4
ns
SDA0 and SCL0 signal rise time
t
R
1000
20 + 0.1Cb
Note 5
300
ns
SDA0 and SCL0 signal fall time
t
F
300
20 + 0.1Cb
Note 5
300
ns
Stop condition setup time
t
SU:STO
4.0
0.6
m
s
Spike pulse width controlled by input filter
t
SP
0
50
ns
Capacitive load per each bus line
Cb
400
400
pF
Notes 1.
On start condition, the first clock pulse is generated after this period.
2.
To fulfill undefined area of the SCL0 falling edge, it is necessary for the device to provide internally
SDA0 signal (on V
IHmin.
of SCL0 signal) with at least 300 ns of hold time.
3.
If the device does not extend the SCL0 signal low hold time (t
LOW
), only maximum data hold time
(t
HD:DAT
) needs to be fulfilled.
4.
The high-speed mode I
2
C bus is available in the standard mode I
2
C bus system. At this time, the
conditions described below must be satisfied.
If the device does not extend the SCL0 signal low state hold time
t
SU:DAT
> 250 ns
If the device extends the SCL0 signal low state hold time
Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (t
Rmax.
+
t
SU:DAT
= 1000 + 250 = 1250 ns by standard mode I
2
C bus specification).
5.
Cb : total capacitance per one bus line (unit : pF)
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