
31
LIST OF FIGURES (7/8)
Figure No.
Title
Page
19-12.
19-13.
19-14.
19-15.
3-Wire Serial I/O Mode Timing ......................................................................................................
Circuit of Switching in Transfer Bit Order ......................................................................................
Reception Completion Interrupt Request Generation Timing (when ISRM = 1)............................
Receive Buffer Register Read Disable Period ..............................................................................
472
473
474
475
20-1.
20-2.
20-3.
20-4.
20-5.
Real-time Output Port Block Diagram ...........................................................................................
Real-time Output Buffer Register Configuration ............................................................................
Port Mode Register 12 Format ......................................................................................................
Real-time Output Port Mode Register Format ...............................................................................
Real-time Output Port Control Register Format ............................................................................
478
479
480
480
481
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
21-15.
21-16.
21-17.
21-18.
21-19.
21-20.
21-21.
Basic Configuration of Interrupt Function ......................................................................................
Interrupt Request Flag Register Format........................................................................................
Interrupt Mask Flag Register Format.............................................................................................
Priority Specify Flag Register Format............................................................................................
External Interrupt Mode Register 0 Format ...................................................................................
External Interrupt Mode Register 1 Format ...................................................................................
Sampling Clock Select Register Format........................................................................................
Noise Eliminator Input/Output Timing (during rising edge detection) ............................................
Program Status Word Configuration .............................................................................................
Flowchart of Generation from Non-Maskable Interrupt Request to Acknowledgment...................
Non-Maskable Interrupt Request Acknowledge Timing.................................................................
Non-Maskable Interrupt Request Acknowledge Operation ...........................................................
Interrupt Request Acknowledge Processing Algorithm..................................................................
Interrupt Request Acknowledge Timing (Minimum Time) ..............................................................
Interrupt Request Acknowledge Timing (Maximum Time) .............................................................
Multiple Interrupt Example.............................................................................................................
Interrupt Request Hold ..................................................................................................................
Basic Configuration of Test Function .............................................................................................
Format of Interrupt Request Flag Register 1L...............................................................................
Format of Interrupt Mask Flag Register 1L....................................................................................
Key Return Mode Register Format................................................................................................
486
489
490
491
492
493
494
495
496
498
498
499
501
502
502
504
506
507
508
508
509
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
Memory Map when Using External Device Expansion Function...................................................
Memory Expansion Mode Register Format...................................................................................
Memory Size Switching Register Format ......................................................................................
Instruction Fetch from External Memory .......................................................................................
External Memory Read Timing ......................................................................................................
External Memory Write Timing ......................................................................................................
External Memory Read Modify Write Timing .................................................................................
Connection Example of
μ
PD78054 and Memory ..........................................................................
512
516
517
519
520
521
522
523
23-1.
23-2.
Oscillation Stabilization Time Select Register Format ...................................................................
HALT Mode Clear upon Interrupt Request Generation .................................................................
526
528