參數(shù)資料
型號： 0W888-002-XTP
廠商： ON Semiconductor
文件頁數(shù)： 23/30頁
文件大?。?/td> 0K
描述： DSP BELASIGNA 250 AUDIO 64LFBGA
標準包裝： 1,500
系列： BelaSigna® 250
類型： 音頻處理器
應(yīng)用： 便攜式設(shè)備
安裝類型： 表面貼裝
封裝/外殼： 64-LFBGA
供應(yīng)商設(shè)備封裝： 64-LFBGA（7x7）
包裝： 帶卷 (TR)
BELASIGNA 250
http://onsemi.com
3
Electrical Performance Specifications
The parameters in Table 2 do not vary with WOLA filterbank configuration. The tests were performed at 20
°C with a clean
1.8 V supply voltage. BELASIGNA 250 was running in high voltage mode (VDDC = 1.8 V). The system clock (SYS_CLK)
was set to 5.12 MHz and a sampling frequency of 16 kHz was used with MCLK was set to 1.28 MHz.
Parameters marked as screened are tested on each chip. Other parameters are qualified but not tested on every part.
Table 2. ELECTRICAL SPECIFICATIONS
Description
Symbol
Conditions
Min
Typ
Max
Units
Screened
OVERALL
Supply voltage
VBAT
0.9
(Note 3)
1.8
2.0
V
Current consumption
IBAT
SYS_CLK = 1.28 MHz,
sample rate = 16 kHz
650
mA
5.12 MHz, 16 kHz
1
mA
19.2 MHz, 16 kHz
5
mA
49.152 MHz, 16 kHz
10
mA
49.152 MHz, 48 kHz
13
mA
VREG (1 mF External Capacitor)
Regulated voltage output
VREG
0.95
1.00
1.05
V
√
Regulator PSRR
VREG_PSRR
1 kHz
50
55
dB
Load current
ILOAD
2
mA
Load regulation
LOADREG
11
20
mV/mA
Line regulation
LINEREG
2
5
mV/V
VDBL (1 mF External Capacitor)
Regulated doubled voltage output
VDBL
1.9
2.0
2.1
V
√
Regulator PSRR
VDBLPSRR
1 kHz
45
50
dB
Load current
ILOAD
2
mA
Load regulation
LOADREG
120
200
mV/mA
√
Line regulation
LINEREG
5
10
mV/V
VDDC (1 mF External Capacitor)
Digital supply voltage output
VDDC
LV mode (VREG)
0.9
1.0
1.1
V
√
DV mode (VDBL)
1.8
2.0
2.2
V
√
Regulator PSRR
VDDCPSRR
LV mode; 1 kHz
20
28
dB
DV mode; 1 kHz
40
48
dB
Load current
ILOAD
All modes
3.5
mA
VDDC (1 mF External Capacitor)
Load regulation
LOADREG
LV mode
5
10
mV/mA
√
DV mode
150
250
mV/mA
√
Line regulation
LINEREG
LV mode
1.5
10
mV/V
DV mode
5
10
mV/V
POWERONRESET (POR)
POR startup voltage
VDDCSTARTUP
0.78
0.83
0.88
V
POR shutdown voltage
VDDCSHUTDOWN
0.76
0.81
0.86
V
3. Audio performance will be degraded below 1.05 V.
4. Measured with a = 12 dB input signal.
5. Input stage delay is inversely proportional to sampling frequency.
6. Max voltage should be limited to 2.2 V peak regardless of VDDC. Protection diodes will be enabled above this voltage.
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