參數(shù)資料
型號(hào): 101-0517
廠商: Rabbit Semiconductor
文件頁(yè)數(shù): 7/110頁(yè)
文件大?。?/td> 0K
描述: MODULE RABBITCORE RCM3100
標(biāo)準(zhǔn)包裝: 1
系列: RabbitCore®
模塊/板類型: MPU 核心模塊
適用于相關(guān)產(chǎn)品: RCM3100
其它名稱: 316-1021
98
RabbitCore RCM3100
Quad Decode Control
Register
QDCR
Address = 10010001 (0x91)
Bit
Value
Description
7:6
0x
Disable Quadrature Decoder 2 inputs. Writing a new
value to these bits will not cause Quadrature
Decoder 2 to increment or decrement.
10
Quadrature Decoder 2 inputs from Port F bits 3 and
2.
11
Quadrature Decoder 2 inputs from Port F bits 7 and
6.
5:4
xx
These bits are ignored.
3:2
0x
Disable Quadrature Decoder 1 inputs. Writing a new
value to these bits will not cause Quadrature
Decoder 1 to increment or decrement.
10
Quadrature Decoder 1 inputs from Port F bits 1 and
0.
11
Quadrature Decoder 1 inputs from Port F bits 5 and
4.
1:0
0
Quadrature Decoder interrupts are disabled.
1
Quadrature Decoder interrupt use Interrupt Priority
1.
10
Quadrature Decoder interrupt use Interrupt Priority
2.
11
Quadrature Decoder interrupt use Interrupt Priority
3.
Quad Decode Count Register
QDC1R
Address = 10010100 (0x94)
(QDC2R)
Address = 10010110 (0x96)
Bit(s)
Value
Description
7:0
read
The current value of the Quadrature Decoder
counter is reported.
Table E-5. Quadrature Decoder Registers (continued)
Register Name
Mnemonic
Address
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