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參數(shù)資料
| 型號(hào)： | 101-0521 |
| 廠商： | Rabbit Semiconductor |
| 文件頁(yè)數(shù)： | 30/138頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MODULE RABBITCORE RCM3210 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | RabbitCore® |
| 模塊/板類(lèi)型： | MPU 核心模塊 |
| 適用于相關(guān)產(chǎn)品： | RCM3210 |
| 其它名稱(chēng)： | 101-521 101-521-ND |
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User’s Manual
119
E.3 Using Parallel Port F
Parallel Port F is a byte-wide port with each bit programmable for data direction and drive.
These are simple inputs and outputs controlled and reported in the Port F Data Register.
As outputs, the bits of the port are buffered, with the data written to the Port F Data Regis-
ter transferred to the output pins on a selected timing edge. The outputs of Timer A1,
Timer B1, or Timer B2 can be used for this function, with each nibble of the port having a
separate select field to control this timing. These inputs and outputs are also used for
access to other peripherals on the chip.
As outputs, Parallel Port F can carry the four Pulse Width Modulator outputs on PF4–PF 7
(J6, pins 5–8). As inputs, Parallel Port F can carry the inputs to the Quadrature Decoders
on PF0–PF3 (J6, pins 1–4). When Serial Port C or Serial Port D is used in clocked serial
mode, two pins of Port F (PF0 / J6:1 and PF1 / J6:2) are used to carry the serial clock sig-
nals. When the internal clock is selected in these serial ports, the corresponding bit of Par-
allel Port F is set as an output.
E.3.1 Parallel Port F Registers
Data Direction Register—PFDDR, address 00111111 (0x3F), write-only, default value on
reset 00000000. For each bit position, write a 1 to make the corresponding port line an
output, or 0 to produce an input.
Drive Control Register—PFDCR, address 00111110 (0x3E), Write-only, no default on
reset (port defaults to all inputs). Effective only if the corresponding port bits are set as
outputs, each bit set to 1 configures the corresponding port bit as open drain. Setting the
bit to 0 configures that output as active high or low.
Function Register—PFFR, address 00111101 (0x3D), Write-only, no default on reset.
This register sets the alternate output function assigned to each of the pins of the port.
When set to 0, the corresponding port pin functions normally as an output (if configured to
be an output in PFDDR). When set to 1, each bit sets the corresponding pin to have the
alternate output function as shown in the summary table at the end of this section.
Control Register—PFCR, address 00111100 (0x3C), Write-only, default on reset
xx00xx00. This register sets the transfer clock, which controls the timing of the outputs on
each nibble of the output ports to allow close synchronization with other events. The sum-
mary table at the end of this section shows the settings for this register. The default values
on reset transfer the output values on CLK/2.
Data Register—PFDR, address 00111000 (0x38), Read or Write, no default value on
reset. On read, the current state of the pins is reported. On write, the output buffer is writ-
ten with the value for transfer to the output port register on the next rising edge of the
transfer clock, set in the PFCR.
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