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參數(shù)資料
| 型號： | 16LF628A |
| 廠商： | Microchip Technology Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | FLASH-Based 8-Bit CMOS Microcontrollers |
| 中文描述： | 基于閃存的8位CMOS微控制器 |
| 文件頁數(shù)： | 100/168頁 |
| 文件大?。?/td> | 3760K |
| 代理商： | 16LF628A |
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PIC16F627A/628A/648A
DS40044A-page 98
Preliminary
2002 Microchip Technology Inc.
14.4
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOR)
14.4.1
POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in RESET until
V
DD
has reached a high enough level for proper oper-
ation. To take advantage of the POR, just tie the MCLR
pin through a resistor to V
DD
. This will eliminate exter-
nal RC components usually needed to create Power-on
Reset. A maximum rise time for V
DD
is required. See
Electrical Specifications for details.
The POR circuit does not produce an internal RESET
when V
DD
declines.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating con-
ditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting”.
14.4.2
POWER-UP TIMER (PWRT)
The PWRT provides a fixed 72 ms (nominal) time out
on power-up (POR) or if enabled from a Brown-out
Reset. The PWRT operates on an internal RC oscilla-
tor. The chip is kept in RESET as long as PWRT is
active. The PWRT delay allows the V
DD
to rise to an
acceptable level. A configuration bit, PWRTE can
disable (if set) or enable (if cleared or programmed) the
PWRT. It is recommended that the PWRT be enabled
when Brown-out Reset is enabled.
The Power-Up Time delay will vary from chip to chip
and due to V
DD
, temperature and process variation.
See DC parameters Table 17-7 for details.
14.4.3
OSCILLATOR START-UP TIMER
(OST)
The OST provides a 1024 oscillator cycle (from OSC1
input) delay after the PWRT delay is over. Program
execution will not start until the OST time out is com-
plete. This ensures that the crystal oscillator or resona-
tor has started and stabilized.
The OST time out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP. See Table 17-7.
14.4.4
BROWN-OUT RESET (BOR)
The PIC16F627A/628A/648A have on-chip BOR cir-
cuitry. A configuration bit, BOREN, can disable (if clear/
programmed) or enable (if set) the BOR Reset circuitry.
If V
DD
falls below V
BOR
for longer than T
BOR
, the
brown-out situation will RESET the chip. A RESET is
not guaranteed to occur if V
DD
falls below V
BOR
for
shorter than T
BOR
. V
BOR
and T
BOR
are defined in
Table 17-2 and Table 17-7, respectively.
On any RESET (Power-on, Brown-out, Watchdog,
etc.), the chip will remain in RESET until V
DD
rises
above BV
DD
(see Figure 14-7). The Power-up Timer
will now be invoked, if enabled, and will keep the chip
in RESET an additional 72 ms.
If V
DD
drops below V
BOR
while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once V
DD
rises above V
BOR
, the Power-Up Timer will execute a
72 ms RESET. Figure 14-7 shows typical Brown-out
situations.
FIGURE 14-7:
BROWN-OUT SITUATIONS WITH PWRT ENABLED
72 ms
V
BOR
V
DD
INTERNAL
RESET
V
BOR
V
DD
INTERNAL
RESET
72 ms
<72 ms
72 ms
V
BOR
V
DD
INTERNAL
RESET
≥
T
BOR
Note:
72 ms delay only if PWRTE bit is programmed to ‘0’.
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