參數(shù)資料
型號： 16LF628A
廠商： Microchip Technology Inc.
元件分類： 8位微控制器
英文描述： FLASH-Based 8-Bit CMOS Microcontrollers
中文描述： 基于閃存的8位CMOS微控制器
文件頁數(shù)： 20/168頁
文件大?。?/td> 3760K
代理商： 16LF628A
PIC16F627A/628A/648A
DS40044A-page 18
Preliminary
2002 Microchip Technology Inc.
4.2.2
SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and Periph-
eral functions for controlling the desired operation of
the device (Table 4-3). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.
TABLE 4-3:
SPECIAL REGISTERS SUMMARY BANK0
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Reset
(1)
Details
on
Page
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
28
01h
TMR0
Timer0 module’s Register
xxxx xxxx
45
02h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
28
03h
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
22
04h
FSR
Indirect data memory address pointer
xxxx xxxx
28
05h
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx 0000
31
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
36
07h
—
Unimplemented
—
—
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
0Ah
PCLATH
—
—
—
Write buffer for upper 5 bits of program counter
---0 0000
28
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
24
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000
26
0Dh
—
Unimplemented
—
—
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1
xxxx xxxx
48
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1
xxxx xxxx
48
10h
T1CON
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
--00 0000
48
11h
TMR2
TMR2 module’s register
0000 0000
52
12h
T2CON
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
52
13h
—
Unimplemented
—
—
14h
—
Unimplemented
—
—
15h
CCPR1L
Capture/Compare/PWM register (LSB)
xxxx xxxx
55
16h
CCPR1H
Capture/Compare/PWM register (MSB)
xxxx xxxx
55
17h
CCP1CON
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
55
18h
RCSTA
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D
0000 000x
69
19h
TXREG
USART Transmit data register
0000 0000
76
1Ah
RCREG
USART Receive data register
0000 0000
79
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
1Eh
—
Unimplemented
—
—
1Fh
Legend:
CMCON
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000
61
Note
1:
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