參數(shù)資料
型號: 20-101-0526
廠商: Rabbit Semiconductor
文件頁數(shù): 39/142頁
文件大小: 0K
描述: COMPUTER SNGLBD LP3510 FOX7.4MHZ
標準包裝: 1
系列: SBC
模塊/板類型: 單板計算機模塊
適用于相關產(chǎn)品: LP3510
User’s Manual
127
E.2.3 Reset Generator
The LP3500 module uses a reset generator on the module, U11, to reset the Rabbit 3000
microprocessor when the voltage drops below the voltage necessary for reliable operation.
The reset occurs between 2.55 V and 2.75 V, typically 2.63 V.
E.3 Chip Select Circuit
The current drain on the battery in a battery-backed circuit must be kept at a minimum.
When the LP3500 is not powered, the battery keeps the SRAM memory contents and the
real-time clock (RTC) going. The SRAM has a powerdown mode that greatly reduces
power consumption. This powerdown mode is activated by raising the chip select (CS)
signal line. Normally the SRAM requires Vcc to operate. However, only 2 V is required
for data retention in powerdown mode. Thus, when power is removed from the circuit, the
battery voltage needs to be provided to both the SRAM power pin and to the CS signal
line. The CS control circuit accomplishes this task for the SRAM’s chip select signal line.
In a powered-up condition, the CS control circuit must allow the processor’s chip select
signal /CS1 to control the SRAM’s CS signal /CSRAM. So, with power applied, /CSRAM
must be the same signal as /CS1, and with power removed, /CSRAM must be held high
(but only needs to be battery voltage high).The isolated /CSRAM line has a 220 k
pullup
resistor to VRAM (R46). This pullup resistor keeps /CSRAM at the VRAM voltage level
(which under no power condition is the backup battery’s regulated voltage at a little more
than 2 V).
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