參數(shù)資料
型號(hào): 2064VL
廠商: Lattice Semiconductor Corporation
英文描述: 2.5V In-System Programmable SuperFAST⑩ High Density PLD
中文描述: 2.5V的在系統(tǒng)可編程超快⑩高密度可編程邏輯器件
文件頁數(shù): 4/14頁
文件大?。?/td> 188K
代理商: 2064VL
4
Specifications
ispLSI 2064VL
Switching Test Conditions
V
CC
R1
R2
CL
*
Device
Output
Test
Point
*
CL includes Test Fixture and Probe Capacitance.
0213A/2064VL
Figure 2. Test Load
DC Electrical Characteristics
Over Recommended Operating Conditions
V
OL
SYMBOL
1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at V
CC
= 2.5V and T
A
= 25
°
C.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I
CC
.
5. With no pull-up resistors.
Table 2-0007/2064VL
1
5
V
OH
I
IH
I
IL-isp
I
IL-PU
I
OS
I
CC
I
IL
PARAMETER
2, 4
Output Low Voltage
Output High Voltage
Input or I/O High Leakage Current
BSCAN
Input Pull-Up Current
I/O Active Pull-Up Current
Output Short Circuit Current
Input or I/O Low Leakage Current
Operating Power Supply Current
I
OL
= 100
μ
A
I
OL
= 8mA
I
OH
= -100
μ
A
0V
V
V (Max.)
IN
V
IH
(min)
V
IN
3.6V
0V
V
V
0V
V
V
V = 2.5V, V = 0.5V
V = 0.0V, V = 2.5V
f = 1 MHz
IN
IL
IN
IL
CONDITION
MIN.
TYP.
MAX.
0.2
UNITS
V
3
2.0
1.8
60
10
-150
-150
-100
-10
V
V
μ
A
μ
A
μ
A
mA
μ
A
mA
I
OH
= -1mA
I
OH
= -4mA
V
CC
- 0.2
V
0.4
V
Input Pulse Levels
Table 2-0003/2064VL
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to V
CC
1.5 ns 10% to 90%
V
CC
/2
V
CC
/2
See Figure 2
3-state levels are measured 0.15V from
steady-state active level.
TEST CONDITION
R1
250
250
R2
218
218
CL
35pF
35pF
35pF
A
B
Active High
Active Low
Active High to Z
at
V
OH
C
250
5pF
218
5pF
Active Low to Z
at
V
OL
Table 2-0004/2064VL
Output Load Conditions (see Figure 2)
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