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參數(shù)資料
| 型號(hào)： | 24FC65-ISM |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 中文描述： | 64K的5.0V 1兆赫的I 2 C串行EEPROM智能 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 140K |
| 代理商： | 24FC65-ISM |
1996 Microchip Technology Inc.
DS21125B-page 5
24FC65
3.6
Device Addressing
A control byte is the first byte received following the
START from the master device. The control byte consists
of a four bit control code, for the 24FC65 this is set as
1010 binary for read and write operations. The next three
bits of the control byte are the device select bits (A2, A1,
A0). They are used by the master device to select which
of the eight devices are to be accessed. These bits are
in effect the three most significant bits of the word
address. The last bit of the control byte (R/W) defines the
operation to be performed. When set to a one a read
operation is selected, when set to a zero a write opera-
tion is selected. The next two bytes received define the
address of the first data byte (Figure 4-1). Because only
A12..A0 are used, the upper three address bits must be
zeros. The most significant bit of the most significant byte
is transferred first. Following the START, the 24FC65
monitors the SDA bus checking the device type identifier
being transmitted. Upon receiving a 1010 code and
appropriate device select bits, the slave device (24FC65)
outputs an acknowledge signal on the SDA line.
Depending upon the state of the R/W bit, the 24FC65 will
select a read or write operation.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
Operation
Control
Code
Device Select
R/W
Read
1010
Device Address
1
Write
1010
Device Address
0
SLAVE ADDRESS
X = Don’t care
1
0
1
0
A2
A1
A0
R/W
A
START
READ/WRITE
4.0
WRITE OPERATION
4.1
Byte Write
Following the START from the master, the control code
(four bits), the device select (three bits), and the R/W bit
which is a logic low is placed onto the bus by the master
transmitter. This indicates to the addressed slave
receiver (24FC65) that a byte with a word address will
follow after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmitted
by the master is the high-order byte of the word address
and will be written into the address pointer of the
24FC65. The next byte is the least significant address
byte. After receiving another acknowledge signal from
the 24FC65 the master device will transmit the data word
to be written into the addressed memory location. The
24FC65 acknowledges again and the master generates
a STOP. This initiates the internal write cycle, and during
this time the 24FC65 will not generate acknowledge sig-
nals (Figure 4-1).
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24FC65 in the same way as
in a byte write. But instead of generating a STOP the
master transmits up to eight pages of eight data bytes
each (64 bytes total) which are temporarily stored in the
on-chip page cache of the 24FC65. They will be written
from the cache into the EEPROM array after the master
has transmitted a STOP. After the receipt of each word,
the six lower order address pointer bits are internally
incremented by one. The higher order seven bits of the
word address remain constant. If the master should
transmit more than eight bytes prior to generating the
STOP (writing across a page boundary), the address
counter (lower three bits) will roll over and the pointer will
be incremented to point to the next line in the cache. This
can continue to occur up to eight times or until the cache
is full, at which time a STOP should be generated by the
master. If a STOP is not received, the cache pointer will
roll over to the first line (byte 0) of the cache, and any
further data received will overwrite previously captured
data. The STOP can be sent at any time during the
transfer. As with the byte write operation, once the STOP
is received an internal write cycle will begin. The 64 byte
cache will continue to capture data until a STOP occurs
or the operation is aborted (Figure 4-2).
FIGURE 4-1:
BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE
WORD
ADDRESS (1)
A
C
K
S
T
A
R
T
WORD
ADDRESS (0)
A
C
K
A
C
K
0
S
T
O
P
A
C
K
0 0
DATA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 24FC65-P | 64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC65-SM | 64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC65 | 64K 5.0V 1MHz CMOS Smart Serial EEPROMs(4.5~5.5V,64K位,10M次擦寫周期,IIC智能串行EEPROM) |
| 24HCA | surface mount silicon Zener diodes |
| 24HCB | surface mount silicon Zener diodes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24FC65-P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC65-SM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC65T-/P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K 5.0V 1 MHz I2C⑩ Smart Serial⑩ EEPROM |
| 24FC65T-/SM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K 5.0V 1 MHz I2C⑩ Smart Serial⑩ EEPROM |
| 24FC65T-I/P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K 5.0V 1 MHz I2C⑩ Smart Serial⑩ EEPROM |
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