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參數(shù)資料
| 型號： | 24FC65-ISM |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 中文描述： | 64K的5.0V 1兆赫的I 2 C串行EEPROM智能 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 140K |
| 代理商： | 24FC65-ISM |
1996 Microchip Technology Inc.
DS21125B-page 9
24FC65
7.0
PAGE CACHE AND ARRAY
MAPPING
The cache is a 64 byte (8 pages x 8 bytes) FIFO buffer.
The cache allows the loading of up to 64 bytes of data
before the write cycle is actually begun, effectively
providing a 64-byte burst write at the maximum bus
rate. Whenever a write command is initiated, the cache
starts loading and will continue to load until a stop bit is
received to start the internal write cycle. The total
length of the write cycle will depend on how many
pages are loaded into the cache before the stop bit is
given. Maximum cycle time for each page is 5 ms. Even
if a page is only partially loaded, it will still require the
same cycle time as a full page. If more than 64 bytes of
data are loaded before the stop bit is given, the address
pointer will'wrap around' to the beginning of cache
page 0 and existing bytes in the cache will be
overwritten. The device will not respond to any
commands while the write cycle is in progress.
7.1
Cache Write Starting at a Page
Boundary
If a write command begins at a page boundary
(address bits A2, A1 and A0 are zero), then all data
loaded into the cache will be written to the array in
sequential addresses. This includes writing across a
4K block boundary. In the example shown below,
(Figure 7-1) a write command is initiated starting at
byte 0 of page 3 with a fully loaded cache (64 bytes).
The first byte in the cache is written to byte 0 of page 3
(of the array), with the remaining pages in the cache
written to sequential pages in the array. A write cycle is
executed after each page is written. Since the write
begins at page 3 and 8 pages are loaded into the
cache, the last 3 pages of the cache are written to the
next row in the array.
7.2
Cache Write Starting at a Non-Page
Boundary
When a write command is initiated that does not begin
at a page boundary (i.e., address bits A2, A1 and A0
are not all zero), it is important to note how the data is
loaded into the cache, and how the data in the cache is
written to the array. When a write command begins, the
first byte loaded into the cache is always loaded into
page 0. The byte within page 0 of the cache where the
load begins is determined by the three least significant
address bits (A2, A1, A0) that were sent as part of the
write command. If the write command does not start at
byte 0 of a page and the cache is fully loaded, then the
last byte(s) loaded into the cache will roll around to
page 0 of the cache and fill the remaining empty bytes.
If more than 64 bytes of data are loaded into the cache,
data already loaded will be overwritten. In the example
shown in Figure 7-2, a write command has been
initiated starting at byte 2 of page 3 in the array with a
fully loaded cache of 64 bytes. Since the cache started
loading at byte 2, the last two bytes loaded into the
cache wil l ’roll over' and be loaded into the first two
bytes of page 0 (of the cache). When the stop bit is
sent, page 0 of the cache is written to page 3 of the
array. The remaining pages in the cache are then
loaded sequentially to the array. A write cycle is
executed after each page is written. If a partially loaded
page in the cache remains when the STOP bit is sent,
only the bytes that have been loaded will be written to
the array.
7.3
Power Management
The design incorporates a power standby mode when
not in use and automatically powers off after the normal
termination of any operation when a stop bit is received
and all internal functions are complete. This includes
any error conditions, i.e. not receiving an acknowledge
or STOP per the two-wire bus specification. The device
also incorporates V
DD
monitor circuitry to prevent inad-
vertent writes (data corruption) during low-voltage con-
ditions. The V
DD
monitor circuitry is powered off when
the device is in standby mode in order to further reduce
power consumption.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 24FC65-P | 64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC65-SM | 64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC65 | 64K 5.0V 1MHz CMOS Smart Serial EEPROMs(4.5~5.5V,64K位,10M次擦寫周期,IIC智能串行EEPROM) |
| 24HCA | surface mount silicon Zener diodes |
| 24HCB | surface mount silicon Zener diodes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24FC65-P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC65-SM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC65T-/P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K 5.0V 1 MHz I2C⑩ Smart Serial⑩ EEPROM |
| 24FC65T-/SM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K 5.0V 1 MHz I2C⑩ Smart Serial⑩ EEPROM |
| 24FC65T-I/P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K 5.0V 1 MHz I2C⑩ Smart Serial⑩ EEPROM |
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