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參數(shù)資料
| 型號： | 24LC256IP |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 256K I 2 C ⑩ CMOS Serial EEPROM |
| 中文描述： | 256K的I 2 C⑩的CMOS串行EEPROM |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 181K |
| 代理商： | 24LC256IP |
24AA256/24LC256
DS21203C-page 6
1998 Microchip Technology Inc.
5.0
DEVICE ADDRESSING
A control byte is the rst byte received following the
start condition from the master device (Figure 5-1). The
control byte consists of a 4-bit control code; for the
24xx256 this is set as 1010 binary for read and write
operations. The next three bits of the control byte are
the chip select bits (A2, A1, A0). The chip select bits
allow the use of up to eight 24xx256 devices on the
same bus and are used to select which device is
accessed. The chip select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1, and A0 pins for the device to respond. These bits
are in effect the three most signicant bits of the word
address.
The last bit of the control byte denes the operation to
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. The next two bytes received dene the
address of the rst data byte (Figure 5-2). Because
only A14…A0 are used, the upper address bit is a don’t
care bit. The upper address bits are transferred rst, fol-
lowed by the less signicant bits.
Following the start condition, the 24xx256 monitors the
SDA bus checking the control byte being transmitted.
Upon receiving a 1010 code and appropriate device
select bits, the slave device outputs an acknowledge
signal on the SDA line. Depending on the state of
the R/W bit, the 24xx256 will select a read or write
operation.
FIGURE 5-1:
CONTROL BYTE FORMAT
5.1
Contiguous Addressing Across
Multiple Devices
The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 2 Mbit
by adding up to eight 24xx256's on the same bus. In
this case, software can use A0 of the control byte as
address bit A15; A1, as address bit A16; and A2, as
address bit A17. It is not possible to read or write
across device boundaries.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
1
0
1
0
A2
A1
A0
SACK
R/W
Control Code
Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
1
010
A
2
A
1
A
0 R/W
X
A
11
A
10
A
9
A
7
A
0
A
8
A
12
CONTROL BYTE
ADDRESS HIGH BYTE
ADDRESS LOW BYTE
CONTROL
CODE
CHIP
SELECT
BITS
X = Don’t Care Bit
A
13
A
14
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24LC256ISM | 制造商:Microchip 功能描述:SHIPS IN 24 HOURS GREEN 制造商:Microchip Technology Inc 功能描述: |
| 24LC256SC/S15K | 制造商:Microchip Technology Inc 功能描述:256K I2C SMARTCARD EE DIE IN WAFFLE PK - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC256SC/W15K | 制造商:Microchip Technology Inc 功能描述:256K I2C SMARTCARD EE WAFER - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC256SC/WF15K | 制造商:Microchip Technology Inc 功能描述:256K I2C SMARTCARD EE WFR ON FR - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC256T-E/MF | 功能描述:電可擦除可編程只讀存儲器 256K 32K X 8 2.5V SER EE EXT RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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