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Publication#
25627
Issue Date:
March 5, 2003
Rev:
A
Amendment/
+3
Implementing a Common Layout for AMD
MirrorBit
TM
and Intel StrataFlash
TM
Memory Devices
Application Note
Overview
This document describes the benefits of designing with
AMD MirrorBit
Flash memory and the ease with
which system designers can layout a board to accom-
modate high-density flash devices from both AMD and
Intel. The layouts shown accept AMD’s single-bit per
cell LV family, AMD’s new two-bit per cell MirrorBit fam-
ily, and Intel StrataFlash
32Mb-128Mb flash memory
devices.
What are AMD MirrorBit Devices
AMD’s patented MirrorBit technology is a breakthrough
flash architecture solution that enables AMD Flash
memory devices to hold twice as much data per tran-
sistor cell as a standard flash product. What’s revolu-
tionary about this accomplishment is that for the first
time, this enhanced density is being delivered without
sacrificing device performance, endurance, and reli-
ability. AMD provides this technology in devices start-
ing at 32Mb density. These products are pinout and
functionally compatible with previous single-bit per cell
LV family devices and provide an easy migration path
from lower density 2 Megabit to 64Megabit LV devices
up to 1 Gigabit MirrorBit devices. For more information
on the specifics of MirrorBit architecture visit the AMD
web site for a comprehensive white paper and online
reference material.
Advantages of Designing with AMD
MirrorBit
AMD’s new MirrorBit technology provides a low-cost,
more reliable alternative to Multi-Level Cell (MLC) so-
lutions. MLC products such as Intel’s StrataFlash suffer
from performance and reliability concerns inherent
when detecting between multiple charge levels in a sin-
gle Flash cell. The following Table 1 provides a com-
parison between AMD’s MirrorBit and Intel’s
StrataFlash device features.
Table 1.
AMD and Intel 64 Mb Flash Memory Comparison
Specification
AMD LV
AMD MirrorBit
Intel
StrataFlash
Notes
Bus Width
x8 only, x8/x16,
and x16 only
x8 only, x8/x16,
and x16 only
x8/x16
Both selectable via BYTE# pin
Core Supply Voltage
2.7–3.6 V
or 3.0–3.6 V
2.7–3.6 V
or 3.0–3.6 V
2.7 V–3.6 V
Same core voltage range
I/O Voltage Range
2.7–3.6 V
or 3.0–3.6 V
1.65 V–3.6 V
2.7 V–3.6 V
AMD features Enhanced V
I/O
range
1.65V - 3.6V
Sector Size
64Kbyte
64Kbyte
128Kbyte
64KB is AMD standard sector size
Random Access Time
90 ns
90 ns
120 ns
Access times unchanged on
MirrorBit technology
Page Access Time
N/A
25 ns
25 ns
Page Length
N/A
4 word
4 word
Word Programming
11us
15 us
13.625 us
MirrorBit and StrataFlash calculated
using write buffer
(See Note)
Sector Erase Time (typ)
1600ms
400 ms
1000 ms
MirrorBit technology improves erase
times for AMD devices
Operating Temp. Range
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C