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| 型號： | 25627A3 |
| 英文描述： | 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs |
| 中文描述： | 實現(xiàn)一個共同的AMD的MirrorBit布局？和英特爾StrataFlash？存儲設(shè)備 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 191K |
| 代理商： | 25627A3 |
Implementing a Common Layout for AMD MirrorBit
TM
and Intel StrataFlash
TM
Memory Devices
7
Command Sets and Software
Compatibility
Designing dual footprints to insure hardware compati-
bility is just one step of implementing a multi-sourced
layout. Just as much emphasis needs to be placed on
software adaptability. AMD and Intel each use different
command sets. AMD uses two to six bus cycle com-
mands to better prevent unintended commands from
being executed due to system noise or errant code ex-
ecution. This method provides an additional level of
software write protection. Most Intel commands require
only two bus write cycles. Figure 3 lists AMD and In-
tel’s equivalent commands for their “Standard Com-
mand Set” in the Address/Data format.
Table 3.
AMD and Intel Pinout Compatibility
For applications that require only minimal Flash opera-
tions such as reading and programming a device and
do not require a highly optimized driver, designers can
choose to implement a flash driver that queries the
flash device identification (ID) and branches to that
vendor’s associated instruction set. In this case a man-
ufacturer ID can be read from internal registers within
the flash device to determine which instruction set to
use. A sample algorithm has been included that en-
ables a flash driver to distinguish between AMD and
Intel devices and branches to the appropriate algo-
rithms.
Device ID Changes on AMD MirrorBit
Devices
AMD’s new generation of LV family devices using the
breakthrough MirrorBit technology are designed to
function as drop-in replacements to the traditional LV
devices. The only modification a design engineer must
take into account is the new 3-byte Device IDs AMD will
implement in this and future generations of flash de-
vices. The 3-byte Device IDs are a change from the tra-
ditional single byte IDs used in the past and will require
the software to use three read-cycles to gather all the
information instead of one (see Figure 5). For a com-
structure, refer to publication number 25538: Migrating
from Single-byte to Three-byte Device IDs Application
Note
, and datasheets posted on www.amd.com.
Write Buffer and Page Read Buffer
Options
A Write Buffer is implemented in MirrorBit flash mem-
ory devices to speed programming operations. The
write buffer is a set of registers that can be used to hold
several words that are to be programmed as a group.
Overall write performance is increased because the
overhead operations required to program each byte or
word are only performed once for the entire group of
words. Similarly, a Page Read Buffer in MirrorBit de-
vices can be used to increase read performance. For
more details on using the Write of Read Buffers, refer
to publication number 25539:
MirrorBit Flash Memory
Write Buffer Programming and Page Buffer Read Ap-
plication Note
.
Command
AMD (Addr/Data)
Intel (Addr/Data)
Read Device ID
5555h/AAh, 2AAAH/55h
5555h/90h
XXXXh/90h
Read (Reset) Mode
XXXXh/F0h
XXXXh/FFh
Sector (Blk) Erase
5555h/AAh, 2AAAh/55h,
5555h/80h, 5555h/AAh,
2AAAh/55h, Blk Addr/30h
Blk Addr/20h,
Blk Addr/D0h
Program (Write)
5555h/AAh, 2AAAh/55h,
5555h/A0h, Addr/Data
Addr/40h,
Addr/Data
Erase Suspend
XXXXh/B0h
XXXXh/B0h
Erase Resume
XXXXh/30h
XXXXh/D0h
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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