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| 型號(hào)： | 25627A3 |
| 英文描述： | 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs |
| 中文描述： | 實(shí)現(xiàn)一個(gè)共同的AMD的MirrorBit布局？和英特爾StrataFlash？存儲(chǔ)設(shè)備 |
| 文件頁(yè)數(shù)： | 4/15頁(yè) |
| 文件大?。?/td> | 191K |
| 代理商： | 25627A3 |
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Implementing a Common Layout for AMD MirrorBit
TM
and Intel StrataFlash
TM
Memory Devices
3
Implementing a Multi-Sourced Layout
Customers wanting to take advantage of the benefits
and savings associated with AMD’s Mirror-Bit technol-
ogy as well as the security of a second source supplier
can implement a multi-sourced board layout. This sec-
tion describes the changes that may be required to en-
able an AMD LV, AMD MirrorBit and Intel StrataFlash
dual-source layout for 32Mb, 64Mb, and 128Mb de-
signs.
Pinout Differences
The AMD LV-Mirror-Bit family and Intel StrataFlash de-
vices are not pin-compatible or drop-in replacements,
however the differences are documented below and in
most cases, they can be worked around. In those
cases where an easy work-around is not possible, this
section helps a design engineer choose a minimal fea-
ture-set common to both product families.
Dual Footprint Layouts
Designing a dual footprint layout is relatively easy with
routing software. As an example, three dual footprint
designs are included. The layouts show that standard
design rules are sufficient: 6/7 mil track and spacing, 10
mil vias (20 mil pad size/10 mil drill size), and 45
°
rout-
ing. The designs are all done with only two routing lay-
ers and separate Power and Ground planes. Although
these layouts can be used as shown, it is highly recom-
mended that system designers develop their own lay-
outs to optimize routing characteristics for their boards.
These layouts were generated using Innoveta’s
(PADS) PowerPCB
design studio. Sample Power-
PCB files, Gerber schematics, and bit-map images can
be obtained from AMD’s website or by contacting your
local AMD sales representative.
Table 2.
AMD and Intel Pinout Compatibility
Feature
AMD Pin(s)
Intel Compatible
Pin(s)
Design Notes
Chip Enable
CE#
CE0, CE1, CE2
Intel’s 3 chip enable pins could potentially replace chip
select logic for cascaded memory arrays for up to eight
devices. Most designers place such chip select logic in
a PLD/ASIC already on board. Connect AMD’s CE pin
to Intel’s CE0 pin and tie CE1 and CE2 to GND.
Status Pin
RY/BY#
STS
In default mode the STS functions like RY/BY. Both are
open-drain outputs and should be tied to V
CC
with a
pull-up resistor.
Hardware Write
Protection
WP#
V
PEN
WP# can be pulled Low to protect first or last two (boot)
sectors of memory. StrataFlash does not have WP#
functionality but does use V
PEN
to protect the entire
device from alteration.
Program Accelerate Pin
ACC
N/A
Intel chose to remove this functionality on its 3V Strata.
AMD uses the WP#/ACC pin as a dual function pin.
Chip Reset
RESET#
RP#
Both pins reset the device and are active low.
I/O Buffer Power
V
IO
V
CCQ
A separate pin for the I/O buffer voltage supply allowing
the device to interface with lower voltage range bus
signals. Available on selected AMD memories.
Address Pins
DQ15/A-1,
A0-A23,
A24-A25
A0,
A1-A24
In Byte mode the AMD DQ15/A-1 pin functions as the
byte selector where Intel uses A0. Remaining pins are
connected in sequence AMD A0-A23 to Intel A1-A24.
AMD supports A24-A25 for densities up to 1Gbit
Data Pins
DQ0–DQ15
DQ0–DQ15
Connect data pins together.
Byte Enable
BYTE#
Byte#
BYTE# selects between Byte Mode (x8) and Word
mode (X16)
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