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參數(shù)資料
| 型號： | 26CV12 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High Performance E2CMOS PLD Generic Array Logic |
| 中文描述： | E2CMOS的可編程邏輯器件的高性能通用陣列邏輯 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 255K |
| 代理商： | 26CV12 |
Specifications
GAL26CV12
13
Vcc
PIN
Vcc
Vref
Active Pull-up
Circuit
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Typical Input
Typical Output
(Vref Typical = 3.2V)
(Vref Typical = 3.2V)
provide a valid power-up reset of the device. First, the V
CC
rise must
be monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation, avoid
clocking the device until all input and feedback path setup times
have been met. The clock must also meet the minimum pulse width
requirements.
Circuitry within the GAL26CV12 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q outputs
set low after a specified time (tpr, 1
μ
s MAX). As a result, the state
on the registered output pins (if they are enabled) will be either high
or low on power-up, depending on the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. Because of the asynchro-
nous nature of system power-up, some conditions must be met to
Vcc
PIN
Vref
Tri-State
Control
Active Pull-up
Circuit
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
Vcc (min.)
t
pr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
t
su
Device Pin
Reset to Logic "0"
Vcc
CLK
INTERNAL REGISTER
Q - OUTPUT
ACTIVE LOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
Power-Up Reset
Input/Output Equivalent Schematics
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