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參數(shù)資料
| 型號： | 26CV12 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High Performance E2CMOS PLD Generic Array Logic |
| 中文描述： | E2CMOS的可編程邏輯器件的高性能通用陣列邏輯 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 255K |
| 代理商： | 26CV12 |
Specifications
GAL26CV12
3
GAL26CV12 OUTPUT LOGIC MACROCELL (OLMC)
Each of the Macrocells of the GAL26CV12 has two primary
functional modes: registered, and combinatorial I/O. The modes
and the output polarity are set by two bits (SO and S1), which are
normally controlled by the logic compiler. Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an
individual product term for each OLMC, and can therefore be
defined by a logic equation. The D flip-flop’s /Q output is fed back
into the AND array, with both the true and complement of the
feedback available as inputs to the AND array.
The GAL26CV12 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two prod-
uct terms are common to all registered OLMCs. The Asynchronous
Reset sets all registered outputs to zero any time this dedicated
product term is asserted. The Synchronous Preset sets all registers
to a logic one on the rising edge of the next clock pulse after this
product term is asserted.
NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.
The GAL26CV12 has a variable number of product terms per
OLMC. Of the twelve available OLMCs, two OLMCs have access
to twelve product terms (pins 20 and 22), two have access to ten
product terms (pins 19 and 23), and the other eight OLMCs have
eight product terms each. In addition to the product terms available
for logic, each OLMC has an additional product term dedicated to
output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.
A R
S P
D
Q
Q
C L K
4 T O 1
M U X
2 T O 1
M U X
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as
registered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Output
tri-state control is available as an individual product term for each
output, and may be individually set by the compiler as either
“
on
”
(dedicated output),
“
off
”
(dedicated input), or
“
product term driven
”
(dynamic I/O). Feedback into the AND array is from the pin side of
the output enable buffer. Both polarities (true and inverted) of the
pin are fed back into the AND array.
Output Logic Macrocell (OLMC)
Output Logic Macrocell Configurations
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