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參數(shù)資料
| 型號(hào)： | 26CV12 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High Performance E2CMOS PLD Generic Array Logic |
| 中文描述： | E2CMOS的可編程邏輯器件的高性能通用陣列邏輯 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 255K |
| 代理商： | 26CV12 |
SSpecifications
GAL26CV12
7
t
pd
t
co
t
cf
2
t
su
1
t
su
2
t
h
A
Input or I/O to Comb. Output
1
7.5
1
10
ns
A
Clock to Output Delay
1
4.5
1
7
ns
—
Clock to Feedback Delay
—
2.5
—
2.5
ns
—
Setup Time, Input or Fdbk before Clk
↑
6
—
7
—
ns
—
Setup Time, SP before Clock
↑
6
—
7
—
ns
—
Hold Time, Input or Fdbk after Clk
↑
0
—
0
—
ns
A
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
95.2
—
71.4
—
MHz
f
max
3
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
117.6
—
105
—
MHz
A
Maximum Clock Frequency with
No Feedback
142.8
—
105
—
MHz
t
wh
t
wl
t
en
t
dis
t
ar
t
arw
t
arr
t
spr
—
Clock Pulse Duration, High
3.5
—
4
—
ns
—
Clock Pulse Duration, Low
3.5
—
4
—
ns
B
Input or I/O to Output Enabled
1
7.5
1
10
ns
C
Input or I/O to Output Disabled
1
7.5
1
9
ns
A
Input or I/O to Asynch. Reset of Reg.
1
9
1
13
ns
—
Asynchronous Reset Pulse Duration
7
—
8
—
ns
—
Asynch. Reset to Clk
↑
Recovery Time
5
—
8
—
ns
—
Synch. Preset to Clk
↑
Recovery Time
5
—
10
—
ns
1) Refer to
Switching Test Conditions
section.
2) Calculated from
f
max with internal feedback. Refer to
fmax Specification
section.
3) Refer to
fmax Specification
section.
PARAM
UNITS
-10
MIN. MAX.
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
C
I
Input Capacitance
8
pF
V
CC
= 5.0V, V
I
= 2.0V
C
I/O
I/O Capacitance
8
pF
V
CC
= 5.0V, V
I/O
= 2.0V
*Characterized but not 100% tested.
IND
COM
-7
MIN.
MAX.
TEST
COND.
1
DESCRIPTION
AC Switching Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
Capacitance (T
A
= 25
°
C, f = 1.0 MHz)
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