
11.0 PCI Bus Interface
CN8236
11.9 Interface Module to Serial EEPROM
ATM ServiceSAR Plus with xBR Traffic Management
11-10
Mindspeed Technologies
28236-DSH-001-A
11.9.3 Accessing the EEPROM
The EEPROM is accessed through the PCI Configuration space at offset 0x4C,
the EEPROM register. See
Section 14.7 for a description of the EEPROM
register’s contents. See
Table 14-16 for a description of register 4C.
Before starting an EEPROM operation, the BUSY bit must be a logic 0 (not
busy). When in this state, the EEPROM can be either written to or read from.
After initiating a read or write operation, the BUSY bit is a logic 1 (busy) until the
transfer completes. During this time, the application software must poll the
BUSY bit to determine when the transfer has completed. Once completed, the
NO_ACK bit indicates the status of the operation. A logic 1 (no acknowledge)
indicates that no device responded to the request.
To initiate a write operation, the application software must write the
BYTE_ADDR and DATA fields and set the READ_WRITE bit to 0. The module
then transfers the data in bits 7:0 (the DATA field) to the device on the bus at the
hardware address at the BYTE_ADDR specified. Application software then polls
the register until the BUSY bit is read as 0 (not busy), which indicates that the
transfer has completed. Software must then check the NO_ACK bit to ensure that
the transaction completed normally. If not, the software should retry the
transaction or signal the error to the user. Since the EEPROM might not respond
until after a few milliseconds after a write transaction, it is recommended that all
operations resulting in NO_ACK = 1 be retried several times before issuing the
failure.
For read operations the application software must also write to the EEPROM
register, specifying the BYTE_ADDR to be read and setting the READ_WRITE
bit to 1. The software must then poll the BUSY bit until the operation completes.
At this point, the data is returned in the DATA field of the EEPROM register. The
software should check the NO_ACK bit to ensure proper completion of the
transfer with no error.
Explanation of series EEPROM clock:
11.9.4 Using the Subsystem ID Without an EEPROM
For applications that can utilize BIOS or boot code to initialize devices before
loading high-level operating system software, the CN8236 allows for the
programming of the PCI Configuration space fields, SUBSYSTEM_ID and
SUBSYSTEM_VENDOR_ID. This feature allows a user to employ the CN8236
without an EEPROM, but still allows for unique Subsystem IDs.
To program the SUBSYSTEM_ID and SUBSYSTEM_VENDOR_ID fields,
BIOS must first write a logic 1 to bit 31 of the PCI Special Status register. This
enables the writing to these two fields in the PCI Configuration space. BIOS can
then update the IDs by writing the desired values to the PCI Configuration space
at offset 0x2C. Once the values are written, BIOS should then disable the writing
to these fields by setting bit 31 of the PCI Special Status register to logic 0. When
bit 31 is set to 0, writes to these two fields are ignored.
SCL
PCI 84
() 4
98.2 KHz @PCI
33MHz
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()
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