CN8236
5.0 Reassembly Coprocessor
ATM ServiceSAR Plus with xBR Traffic Management
5.3 CPCS-PDU Processing
28236-DSH-001-A
Mindspeed Technologies
5-13
5.3.2.1 AAL3/4 Per-Cell
Processing
The following processing steps and checks occur on a per-cell basis:
If the CRC10_EN bit in the AAL3/4 Head VCC table entry is a logic high,
the CRC10 field in the cell is checked. If in error, the SAR increments the
CRC10_ERR counter in the VCC Head table entry, and discards the cell.
The MID field value is checked against active MID values specified by the
MID_BITS and MID0 fields in the AAL3/4 Head VCC table entry. If
invalid, the SAR discards the cell, and increments the MID_ERR counter
in the VCC Head table entry.
If the cell is an EOM cell and LI = 63, the SAR writes a status queue entry
with ABORT bit set, CPCS_LENGTH=0, and BD_PNTR pointing to the
partially reassembled PDU.
If the LI_EN bit in the AAL3/4 Head VCC table entry is a logic high, the
LI field is checked, and the following error detection and error processing
is done:
– If the cell received is a BOM, and LI 44; the SAR discards the cell,
and increments the LI_ERR counter in the VCC Head table entry.
– If the cell received is a COM, and LI 44; the SAR discards the cell,
and terminates the current CPCS-PDU. The SAR also writes a status
queue entry with the LI_ERROR bit set, the CPCS_LENGTH = 0, and
BD_PNTR pointing to the partially reassembled PDU. The SAR also
increments the LI_ERR counter in the VCC Head table entry.
– If the cell received is an EOM, and (LI < 4 or LI > 44); the SAR
discards the cell, and terminates the current CPCS-PDU. The SAR also
writes a status queue entry with the LI_ERROR bit set, the
CPCS_LENGTH = 0, and BD_PNTR pointing to the partially
reassembled PDU. The SAR also increments the LI_ERR counter in the
VCC Head table entry.
– If the cell received is an SSM, and (LI < 8 or LI > 44); the SAR
discards the cell, and increments the LI_ERR counter in the VCC Head
table entry.
If the ST_EN bit in the AAL3/4 Head VCC table entry is a logic high, the
ST field in the cell is checked. The NEXT_ST field in the VCC entry is
used for this check. A value of 01 in the NEXT_ST field indicates that the
SAR was expecting a BOM/SSM cell. An 00 value indicates that the SAR
was expecting a COM/EOM cell. The following error detection and error
processing is done:
– If the cell received is a BOM, and the SAR was expecting a COM or
EOM, the SAR terminates the current CPCS-PDU and writes a status
queue entry with the ST_ERROR bit set, the CPCS_LENGTH = 0, and
the BD_PNTR pointing to the partially reassembled PDU. The SAR
also increments the BOM_SSM_ERR counter in the VCC Head table
entry, and starts a new CPCS-PDU with the current BOM cell.
– If the cell received is an SSM, and the SAR was expecting a COM or
EOM, the SAR terminates the current CPCS-PDU, and writes a status
queue entry with the ST_ERROR bit set, the CPCS_LENGTH =0, and
the BD_PNTR pointing to the partially reassembled PDU. The SAR
also increments the BOM_SSM_ERR counter in the VCC Head table
entry, and processes the current cell as a valid CPCS-PDU.
– If the cell received is a COM, and the SAR was expecting a BOM or
SSM, the SAR discards the cell.