參數(shù)資料
型號: 28C256
英文描述: 32K-Bit Parallel E2PROM
中文描述: 32K的位并行E2PROM的
文件頁數(shù): 13/24頁
文件大?。?/td> 113K
代理商: 28C256
X28C256
13
WRITE CYCLE LIMITS
Symbol
Parameter
Min.
(9)
Typ.
(6)
Max.
Units
t
WC(7)
t
AS
t
AH
t
CS
t
CH
t
CW
t
OES
t
OEH
t
WP
t
WPH
t
WPH2(8)
t
DV
t
DS
t
DH
t
DW
t
BLC(9)
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
CE
Pulse Width
OE
HIGH Setup Time
OE
HIGH Hold Time
WE
Pulse Width
WE
HIGH Recovery
SDP
WE
Recovery
Data Valid
Data Setup
Data Hold
Delay to Next Write
Byte Load Cycle
5
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
μ
s
ns
ns
μ
s
μ
s
3855 PGM T11.1
0
150
0
0
100
10
10
100
50
1
1
50
10
10
1
100
WE
Controlled Write Cycle
3855 FHD F06
Notes:
(6) Typical values are for T
A
= 25
°
C and nominal supply voltage.
(7) t
WC
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
(8) t
WPH
is the normal page write operation
WE
recovery time. t
WPH2
is the
WE
recovery time needed only after the end of issuing
the three-byte SDP command sequence and before writing the first byte of data to the array. Refer to Figure 6 which illustrates
the t
WPH2
requirement.
(9) For faster t
WC
and t
BLC
, refer to X28HC256 or X28VC256.
ADDRESS
tAS
tWC
tAH
tOES
tDV
tDS
tDH
tOEH
CE
WE
OE
DATA IN
DATA OUT
HIGH Z
DATA VALID
tCS
tCH
tWP
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