參數(shù)資料
型號(hào): 28F008B3
廠商: Intel Corp.
英文描述: SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE
中文描述: 智能3高級(jí)啟動(dòng)塊字節(jié)寬
文件頁(yè)數(shù): 28/49頁(yè)
文件大?。?/td> 408K
代理商: 28F008B3
SMART 3 ADVANCED BOOT BLOCK
–BYTE-WIDE
E
28
PRELIMINARY
After any program or block erase operation is
complete (even after V
PP
transitions down to
V
PPLK
), the CUI must be reset to read array mode
via the Read Array command if access to the flash
memory array is desired.
Refer to AP-617 Additional Flash Data Protection
Using V
PP
, RP#, and WP#for a circuit-level
description of how to implement the protection
schemes discussed in Section 3.5.
3.7
Power Supply Decoupling
Flash memory’s power switching characteristics
require
careful
device
designers should consider three supply current
issues:
1.
Standby current levels (I
CCS
)
2.
Active current levels (I
CCR
)
3.
Transient peaks produced by falling and rising
edges of CE#.
decoupling.
System
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 μF ceramic
capacitor connected between each V
CC
and GND,
and between its V
PP
and GND. These high-
frequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.
3.7.1
V
TRACE ON PRINTED CIRCUIT
BOARDS
Designing for in-system writes to the flash memory
requires special consideration of the V
PP
power
supply trace by the printed circuit board designer.
The V
PP
pin supplies the flash memory cells current
for programming and erasing. V
PP
trace widths and
layout should be similar to that of V
CC
. Adequate
V
PP
supply traces, and decoupling capacitors
placed adjacent to the component, will decrease
spikes and overshoots.
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