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參數(shù)資料
| 型號(hào)： | 28F016S3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 V FlashFile Memory(3V閃速存儲(chǔ)器) |
| 中文描述： | 3伏FlashFile內(nèi)存（3V的閃速存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 15/18頁(yè) |
| 文件大?。?/td> | 133K |
| 代理商： | 28F016S3 |
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28F004S3/28F008S3/28F016S3 SPECIFICATION UPDATE
297799-009
February, 1999
11 of 14
After valid data is read, the device must receive another series of CE# glitches (typically
over one hundred) to induce an invalid read.
IMPLICATION:
This erratum may affect read operations in systems that have a lot of
noise on the flash memory’s CE# input. If CE# is generated asynchronously from the
upper address lines, noise on CE# can sometimes occur when upper address lines
transition from one state to another. However, applications that access flash memory
sequentially will have stable upper address lines and will therefore produce fewer CE#
glitches. Systems that execute code from flash memory or download code from flash
memory into DRAM will usually access the device sequentially; therefore, they will be
less susceptible to this erratum.
Carefully analyze the flash memory CE# input. If glitches are detected, more in-depth
system characterization is need to identify susceptibility to this erratum.
It is important to understand how these glitches manifest themselves in order to
determine whether or not they will cause a problem.
1. In systems that flow unlatched addresses to CE# control logic, the decode logic may
generate CE# glitches when the address bus transitions from one state to another.
However, the processor’s address switching frequency is usually very fast
(somewhere in the order of 1/2 the processor’s operating frequency) which will
cause the glitches high time to be less than 145 ns. If the CE#-high time is less than
145 ns, the glitch has no effect on the component.
Note: Most processor’s with integrated chip select logic use latched outputs and
therefore may not have CE# glitches.
2. If the address bus is not pulled up or pulled down during idle bus cycles, the address
bus may be left in an undetermined state. This condition may cause CE# glitches.
WORKAROUND:
If it is determined that the CE# causes a problem, possible solutions to
help workaround this erratum are suggested as follows.
Hardware solution:
Add system logic to prevent CE# glitches such as latched CE# control logic or
pullup/pulldown resistors to the address bus.
Software solution for data storage applications:
If the device receives over one hundred consecutive CE# glitches, issue a Byte
Write command and program FFh to any location before executing a read operation.
Programming FFh will not alter stored data, but it will give the component sufficient
time to prepare for the read operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F008S5 | 8-MBIT 5 VOLT FlashFile Memory(8M位5V閃速存儲(chǔ)器) |
| 28F016S5 | 16-MBIT 5V FlashFile Memory(16M位5V閃速存儲(chǔ)器) |
| 28F008SC | 8-MBIT SmartVoltage FlashFile Memory(8M位智能電壓閃速存儲(chǔ)器) |
| 28F016SC | 16-MBIT SmartVoltage FlashFile Memory(16M位智能電壓閃速存儲(chǔ)器) |
| 28F008S | 8-MBit (1 MBit x 8) FLASHFILE Memory(8-M位 (1 M位 x 8)閃速存儲(chǔ)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F016S5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY 4. 8. AND 16 MBIT |
| 28F016SA | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F016SA 16-MBIT (1 MBIT X 16, 2 MBIT X 8)FlashFile MEMORY |
| 28F016SA/DD28F032SA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INFORMATION |
| 28F016SA-070 | 制造商:undefined 功能描述: |
| 28F016SC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F016SC - BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4. 8. AND 16 MBIT |
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