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參數(shù)資料
| 型號： | 28F400BX-TB |
| 廠商： | Intel Corp. |
| 英文描述： | 4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 4兆位（256 × 16，為512k × 8）啟動塊閃存系列 |
| 文件頁數(shù)： | 26/49頁 |
| 文件大?。?/td> | 427K |
| 代理商： | 28F400BX-TB |
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SMART 3 ADVANCED BOOT BLOCK
–WORD-WIDE
E
26
PRELIMINARY
3.3
Block Locking
The Smart 3 Advanced Boot Block flash memory
architecture
features
parameter blocks so that the kernel code for the
system can be kept secure while other parameter
blocks are programmed or erased as necessary.
two
hardware-lockable
3.3.1
V
= V
FOR COMPLETE
PROTECTION
The V
PP
programming voltage can be held low for
complete write protection of all blocks in the flash
device. When V
is below V
, any program or
erase operation will result in a error, prompting the
corresponding Status Register bit (SR.3) to be set.
3.3.2
WP# = V
IL
FOR BLOCK LOCKING
The lockable blocks are locked when WP# = V
IL
;
any program or erase operation to a locked block
will result in an error, which will be reflected in the
status register. For top configuration, the top two
parameter blocks (blocks #37 and #38 for the
16-Mbit, blocks #21 and #22 for the 8-Mbit, and
blocks #13 and #14 for the 4-Mbit) are lockable. For
the bottom configuration, the bottom two parameter
blocks (blocks #0 and #1 for 4-/8-/16-Mbit) are
lockable. Unlocked blocks can be programmed or
erased normally (unless V
PP
is below V
PPLK
).
3.3.3
WP# = V
IH
FOR BLOCK UNLOCKING
WP# = V
IH
unlocks all lockable blocks.
These blocks can now be programmed or erased.
Note that RP# does not override WP# locking as in
previous Boot Block devices. WP# controls all block
locking and V
PP
provides protection against
spurious writes. Table 8 defines the write protection
methods.
3.4
V
PP
Program and Erase
Voltages
Intel’s Smart 3 products provide in-system
programming and erase at 2.7V–3.6V V
PP
. For
customers requiring fast programming in their
manufacturing environment, Smart 3 includes an
additional
low-cost,
backward-compatible
programming feature.
12V
The 12V V
PP
mode enhances programming
performance during the short period of time typically
found in manufacturing processes; however, it is
not intended for extended use. 12V may be applied
to V
PP
during program and erase operations for a
maximum of 1000 cycles on the main blocks and
2500 cycles on the parameter blocks. V
PP
may be
connected to 12V for a total of 80 hours maximum.
Stressing the device beyond these limits may cause
permanent damage.
Table 8. Write Protection Truth Table for
Advanced Boot Block Flash Memory Family
V
PP
WP#
RP#
Write Protection
Provided
X
X
V
IL
All Blocks Locked
V
IL
X
V
IH
All Blocks Locked
≥
V
PPLK
V
IL
V
IH
Lockable Blocks
Locked
≥
V
PPLK
V
IH
V
IH
All Blocks Unlocked
3.5
Power Consumption
While in operation, the flash device consumes
active power. However, Intel Flash devices have a
three-tiered approach to power savings that can
significantly
reduce
overall
consumption. The Automatic Power Savings (APS)
feature reduces power consumption when the
device is idle. If the CE# is deasserted, the flash
enters
its
standby
consumption is even lower. If RP# = V
IL
the flash
enters a deep power-down mode, where current is
at a minimum. The combination of these features
can minimize overall memory power consumption,
and therefore, overall system power consumption.
system
power
mode,
where
current
3.5.1
ACTIVE POWER
With CE# at a logic-low level and RP# at a logic-
high level, the device is in the active mode. Refer to
the DC Characteristics tables for I
CC
current values.
Active power is the largest contributor to overall
system power consumption. Minimizing the active
current could have a profound effect on system
power consumption, especially for battery-operated
devices.
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