參數(shù)資料
型號(hào)： 28F800C3
廠商： INTEL CORP
元件分類(lèi)： DRAM
英文描述： 3 Volt Advanced Boot Block Flash Memory(3 V 高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器)
中文描述： 16M X 8 FLASH 3V PROM
文件頁(yè)數(shù)： 12/59頁(yè)
文件大?。?/td> 321K
代理商： 28F800C3
28F800C3, 28F160C3, 28F320C3
E
12
PRELIMINARY
3.1.4
RESET
From read mode, RP# at V
IL
for time t
PLPH
deselects the memory, places output drivers in a
high-mpedance state, and turns off all internal
circuits. After return from reset, a time t
PHQV
is
required until the initial read access outputs are
valid. A delay (t
PHWL
or t
PHEL
) is required after
return from reset before a write can be initiated.
After this wake-up interval, normal operation is
restored. The CUI resets to read array mode, the
status register is set to 80H, and all blocks are
locked. This case is shown inFigure 10A
If RP# is taken low for time t
PLPH
during a program
or erase operation, the operation will be aborted
and the memory contents at the aborted location
(for a program) or block (for an erase) are no longer
valid, since the data may be partially erased or
written. The abort process goes through the
following sequence: When RP# goes low, the
device shuts down the operation in progress, a
process which takes time t
PLRH
to complete. After
this time t
PLRH
, the part will either reset to read
array mode (if RP# has gone high during t
PLRH
,
Figure 10B) or enter reset mode (if RP# is still logic
low after t
PLRH
, Figure 10C). In both cases, after
returning from an aborted operation, the relevant
time t
PHQV
or t
PHWL
/t
PHEL
must be observed before
a read or write operation is initiated, as discussed in
the previous paragraph. However, in this case,
these delays are referenced to the end of t
PLRH
rather than when RP# goes high.
Similar to any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, the processor expects to read
from the flash memory. Automated flash memories
provide status information when read during
program or block erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash
memory may be providing status information
instead of array data. Intel
Flash memories allow
proper CPU initialization following a system reset
through the use of the RP# input. In this application,
RP# is controlled by the same RESET# signal that
resets the system CPU.
3.1.5
WRITE
A write takes place when both CE# and WE# are
low and OE# is high. Commands are written to the
Command User Interface (CUI) using standard
microprocessor write timings to control flash
operations. The CUI does not occupy an
addressable memory location. The address and
data buses are latched on the rising edge of the
second WE# or CE# pulse, whichever occurs first.
Figure 9 illustrates a program and erase operation.
The available commands are shown in Table 6, and
Appendix A provides detailed information on
moving between the different modes of operation
using CUI commands.
There are two commands that modify array data:
Program (40H) and Erase (20H). Writing either of
these commands to the internal Command User
Interface (CUI) initiates a sequence of internally-
timed functions that culminate in the completion of
the requested task (unless that operation is aborted
by either RP# being driven to V
IL
for t
PLRH
or an
appropriate suspend command).
3.2
Modes of Operation
The flash memory has four read modes and two
write modes. The read modes are read array, read
configuration, read status, and read query. The
write modes are program and erase. Three
additional modes (erase suspend to program, erase
suspend to read and program suspend to read) are
available only during suspended operations. These
modes
are
reached
summarized in Tables 5 and 6. A comprehensive
chart showing the state transitions is in Appendix A.
using
the
commands
3.2.1
READ ARRAY
When RP# transitions from V
IL
(reset) to V
IH
, the
device defaults to read array mode and will respond
to the read control inputs (CE#, address inputs, and
OE#) without any additional CUI commands.
When the device is in read array mode, four control
signals control data output:
WE# must be logic high (V
IH
)
CE# must be logic low (V
IL
)
OE# must be logic low (V
IL
)
RP# must be logic high (V
IH
)
In addition, the address of the desired location must
be applied to the address pins. If the device is not
in read array mode, as would be the case after a
program or erase operation, the Read Array
command (FFH) must be written to the CUI before
array reads can take place.
相關(guān)PDF資料
PDF描述
28F160C3 3 Volt Advanced Boot Block Flash Memory(3 V 高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器)
28F320D18 1.8 Volt Intel Dual-Plane Flash Memory(1.8 V Intel 雙平面閃速存儲(chǔ)器)
28F320J5 5 Volt Intel StrataFlash Memory(5 V 32M位英特爾StrataFlash存儲(chǔ)器)
28F640J5 5 V Intel StrataFlash Memory(5V 64M位英特爾StrataFlash閃速存儲(chǔ)器)
28F400B3 SMART 3 ADVANCED BOOT BLOCK WORD-WIDE
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28FAN2500_AAA3A862 WAF 制造商:Fairchild Semiconductor Corporation 功能描述:
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