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參數(shù)資料
| 型號(hào)： | 28LV64A-F-30I/L |
| 元件分類： | PROM |
| 英文描述： | 8K X 8 EEPROM 3V, 300 ns, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 130K |
| 代理商： | 28LV64A-F-30I/L |
2004 Microchip Technology Inc.
Preliminary
DS21113E-page 1
FEATURES
2.7V to 3.6V Supply
Read Access Time—300 ns
CMOS Technology for Low Power Dissipation
- 8 mA Active
-50
A CMOS Standby Current
Byte Write Time—3 ms
Data Retention >200 years
High Endurance - Minimum 100,000 Erase/Write
Cycles
Automatic Write Operation
- Internal Control Timer
-
Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
Data Polling
Ready/Busy
Chip Clear Operation
Enhanced Data Protection
-VCC Detector
- Pulse Filter
- Write Inhibit
Electronic Signature for Device Identification
Organized 8Kx8 JEDEC Standard Pinout
- 28-pin Dual-In-Line Package
- 32-pin Chip Carrier (Leadless or Plastic)
Available for Extended Temperature Ranges:
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 28LV64A is a CMOS 64K non-vol-
atile electrically Erasable PROM organized as 8K words by 8 bits.
The 28LV64A is accessed like a static RAM for the read or write
cycles without the need of external components. During a “byte
write”, the address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Fol-
lowing the initiation of write cycle, the device will go to a busy state
and automatically clear and write the latched data using an inter-
nal control timer. To determine when the write cycle is complete,
the user has a choice of monitoring the Ready/Busy output or
using Data polling. The Ready/Busy pin is an open drain output,
which allows easy configuration in ‘wired-or’ systems. Alterna-
tively, Data polling allows the user to read the location last written
to when the write operation is complete. CMOS design and pro-
cessing enables this part to be used in systems where reduced
power consumption and reliability are required. A complete family
of packages is offered to provide the utmost flexibility in applica-
tions.
PACKAGE TYPES
BLOCK DIAGRAM
Pin 1 indicator on PLCC on top of package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RDY/BSY
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
Vcc
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
SS
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
A7
A12
RDY/BSY
NU
Vcc
WE
NC
I/O1
I/O2
Vss
NU
I/O3
I/O4
I/O5
14
15
16
17
18
19
20
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
5
6
7
8
9
10
11
12
13
DI
P/SOIC
PLCC
64K bit
Cell Matrix
Y Gating
Input/Output
Buffers
Data
Poll
Data Protection
Circuitry
Chip Enable/
Output Enable
Control Logic
Auto Erase/Write
Timing
Program Voltage
Generation
Y
Decoder
X
Decoder
L
a
t
c
h
e
s
A0
A12
I
VCC
VSS
CE
OE
WE
Rdy/
Busy
I/O0...................I/O7
28LV64A
64K (8K x 8) Low Voltage CMOS EEPROM
Obsolete Device
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| 28LV64A-FT-20/SO | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K (8K x 8) Low Voltage CMOS EEPROM |
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