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參數(shù)資料
| 型號(hào)： | 28LV64A-F-30I/L |
| 元件分類： | PROM |
| 英文描述： | 8K X 8 EEPROM 3V, 300 ns, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 130K |
| 代理商： | 28LV64A-F-30I/L |
28LV64A
DS21113E-page 4
Preliminary
2004 Microchip Technology Inc.
TABLE 1-4:
BYTE WRITE AC CHARACTERISTICS
FIGURE 1-2:
PROGRAMMING WAVEFORMS
AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:
VIH = 2.0V; VIL = 0.6V; VOH = VOL = VCC/2
1 TTL Load + 100 pF
20 ns
Commercial (C): Tamb =
0
°C to +70°C
Industrial
(I) : Tamb = -40
°C to +85°C
Parameter
Sym
Min
Max
Units
Remarks
Address Set-Up Time
tAS
10
ns
Address Hold Time
tAH
100
ns
Data Set-Up Time
tDS
120
ns
Data Hold Time
tDH
10
ns
Write Pulse Width
tWPL
150
ns
(Note 1)
OE Hold Time
tOEH
10
ns
OE Set-Up Time
tOES
10
ns
Data Valid Time
tDV
1000
ns
(Note 2)
Time to Device Busy
tDB
50
ns
Write Cycle Time (28LV64A)
tWC
3
ms
1.5 ms typical
Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the
positive edge of CE or WE, whichever occurs first.
2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until tDH
after the positive edge of WE or CE, whichever occurs first.
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
twc
tDB
tOEH
tOES
tDH
tDS
tWPL
tAH
tAS
tDV
Busy
Ready
Rdy/Busy
OE
Data In
Address
CE, WE
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