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參數(shù)資料
| 型號： | 29F002B-55 |
| 廠商： | Macronix International Co., Ltd. |
| 英文描述： | 2M-BIT [256K x 8] CMOS FLASH MEMORY |
| 中文描述： | 200萬位[256K × 8]的CMOS閃存 |
| 文件頁數(shù)： | 10/51頁 |
| 文件大小： | 622K |
| 代理商： | 29F002B-55 |
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10
REV. 1.5, MAR. 28, 2005
P/N: PM0547
MX29F002/002N T/B
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all other
conditions. Another Erase Suspend command can be
written after the chip has resumed erasing.
SET-UP AUTOMATIC PROGRAM COMMANDS
To initiate Automatic Program mode, a three-cycle
command sequence is required. There are two "unlock"
write cycles. These are followed by writing the Automatic
Program command A0H.
Once the Automatic Program command is initiated, the
next WE pulse causes a transition to an active programming
operation. Addresses are latched on the falling edge, and
data are internally latched on the rising edge of the WE
pulse. The rising edge of WE also begins the programming
operation. The system does not require to provide further
controls or timings. The device will automatically provide
an adequate internally generated program pulse and verify
margin.
If the program operation was unsuccessful, the data on Q5
is "1", indicating the program operation exceed internal
timing limit. The automatic programming operation is
completed when the data read on Q6 stops toggling for two
consecutive read cycles and the data on Q7 and Q6 are
equivalent to data written to these two bits, at which time
the device returns to the Read mode(no program verify
command is required).
WRITE OPERATION STATUS
DATA POLLING-Q7
The MX29F002T/B also features Data Polling as a method
to indicate to the host system that the Automatic Program
or Erase algorithms are either in progress or completed.
While the Automatic Programming algorithm s n operation,
an attempt to read the device will produce the complement
data of the data last written to Q7. Upon completion of the
Automatic Program Algorithm an attempt to read the
device will produce the true data last written to Q7. The
Data Polling feature is valid after the rising edge of the
fourth WE pulse of the four write pulse sequences for
automatic program.
While the Automatic Erase algorithm is in operation, Q7 will
read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will read
"1". The Data Polling feature is valid after the rising edge
of the sixth WE pulse of six write pulse sequences for
automatic chip/sector erase.
The Data Polling feature s active during Automatic Program/
Erase algorithm or sector erase time-out.(see section Q3
Sector Erase Timer)
Q6:Toggle BIT I
The MX29F002T/B features a "Toggle Bit" as a method to
indicate to the host system that the Auto Program/Erase
algorithms are either in progress or completed.
During an Automatic Program or Erase algorithm operation,
successive read cycles to any address cause Q6 to toggle.
The system may use either OE or CE to control the read
cycles. When the operation is complete, Q6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Q6 toggles and returns
to reading array data. If not all selected sectors are
protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors that
are protected.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase suspended.
When the device is actively erasing (that is, the Automatic
Erase algorithm is in progress), Q6 toggling. When the
device enters the Erase Suspend mode, Q6 stops toggling.
However, the system must also use Q2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use Q7(see the subsection on Q7:Data Polling).
If a program address falls within a protected sector, Q6
toggles for approximately 2 us after the program command
sequence is written, then returns to reading array data.
Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algorithm
is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on Q6. Refer to the toggle bit algorithm.
相關(guān)PDF資料 |
PDF描述 |
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| 29F002B-70 | 2M-BIT [256K x 8] CMOS FLASH MEMORY |
| 29F002B-90 | 2M-BIT [256K x 8] CMOS FLASH MEMORY |
| 29F002T-12 | 2M-BIT [256K x 8] CMOS FLASH MEMORY |
| 29F002T-55 | 2M-BIT [256K x 8] CMOS FLASH MEMORY |
| 29F002T-70 | 2M-BIT [256K x 8] CMOS FLASH MEMORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 29F002B-70 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256K x 8] CMOS FLASH MEMORY |
| 29F002B-90 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256K x 8] CMOS FLASH MEMORY |
| 29F002T-12 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256K x 8] CMOS FLASH MEMORY |
| 29F002T-55 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256K x 8] CMOS FLASH MEMORY |
| 29F002T-70 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256K x 8] CMOS FLASH MEMORY |
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