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參數(shù)資料
| 型號： | 29F022T-90 |
| 廠商： | Macronix International Co., Ltd. |
| 英文描述： | 2M-BIT[256K x 8]CMOS FLASH MEMORY |
| 中文描述： | 200萬位[256K × 8]的CMOS閃存 |
| 文件頁數(shù)： | 7/46頁 |
| 文件大?。?/td> | 606K |
| 代理商： | 29F022T-90 |
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7
P/N:PM0556
REV. 1.3, NOV. 11, 2002
MX29F022/022NT/B
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage. However, multiplexing high voltage onto
address lines is not generally desired system design prac-
tice.
The MX29F022T/B contains a Silicon-ID-Read opera-
tion to supplement traditional PROM programming meth-
odology. The operation is initiated by writing the read
silicon ID command sequence into the command regis-
ter. Following the command write, a read cycle with
A1=VIL, A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of 36H for MX29F022T, 37H for MX29F022B.
Pins
Manufacture code
Device code
for MX29F022T
Device code
for MX29F022B
Chip Protection Verification
A0
VIL
VIH
A1
VIL
VIL
Q7
1
0
Q6
1
0
Q5
0
1
Q4
0
1
Q3
0
0
Q2
0
1
Q1
1
1
Q0
0
0
Code(Hex)
C2H
36H
VIH
VIL
0
0
1
1
0
1
1
1
37H
X
X
VIH
VIH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
01H (Protected)
00H (Unprotected)
TABLE 3. EXPANDED SILICON ID CODE
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero pat-
tern, a self-timed chip erase and verification begin. The
erase and verification operations are completed when
the data on Q7 is "1" at which time the device returns to
the Read mode. The system is not required to provide
any control or timing during these operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verify command is required).
If the Erase operation was unsuccessful, the data on Q5
is "1" (see Table 4), indicating the erase operation of ex-
ceed internal timing limit.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode.
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