參數(shù)資料
型號(hào)： 35007B
廠商： Microchip Technology Inc.
英文描述： 18-pin Enhanced FLASH/EEPROM 8-bit Microcontroller
中文描述： 18針/ EEPROM的8位微控制器的閃存
文件頁(yè)數(shù)： 30/88頁(yè)
文件大?。?/td> 1495K
代理商： 35007B
PIC16F84A
DS35007B-page 28
2001 Microchip Technology Inc.
FIGURE 6-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
DD
):
SLOW V
DD
RISE TIME
6.7
Time-out Sequence and
Power-down Status Bits (TO/PD)
On power-up (Figures 6-6 through 6-9), the time-out
sequence is as follows:
1.
PWRT time-out is invoked after a POR has
expired.
2.
Then, the OST is activated.
The total time-out will vary based on oscillator configu-
ration and PWRTE configuration bit status. For exam-
ple, in RC mode with the PWRT disabled, there will be
no time-out at all.
TABLE 6-5:
TIME-OUT IN VARIOUS
SITUATIONS
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high, execution will begin immediately
(Figure 6-6). This is useful for testing purposes or to
synchronize more than one PIC16F84A device when
operating in parallel.
Table 6-6 shows the significance of the TO and PD bits.
Table 6-3 lists the RESET conditions for some special
registers, while Table 6-4 lists the RESET conditions
for all the registers.
TABLE 6-6:
STATUS BITS AND THEIR
SIGNIFICANCE
V
DD
MCLR
V1
When V
DD
rises very slowly, it is possible that the T
PWRT
time-out and T
OST
time-out will expire before V
DD
has reached its final value. In this example, the chip will reset properly if, and only if, V1
≥
V
DD
min.
INTERNAL POR
T
PWRT
T
OST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
Oscillator
Configuration
Power-up
Wake-up
from
SLEEP
PWRT
Enabled
72 ms +
1024T
OSC
72 ms
PWRT
Disabled
XT, HS, LP
1024T
OSC
1024T
OSC
RC
—
—
TO
PD
Condition
1
1
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT Reset (during normal operation)
WDT Wake-up
MCLR during normal operation
MCLR during SLEEP or interrupt
wake-up from SLEEP
0
x
x
0
0
1
0
0
1
1
1
0
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