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參數(shù)資料
| 型號(hào)： | 35007B |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 18-pin Enhanced FLASH/EEPROM 8-bit Microcontroller |
| 中文描述： | 18針/ EEPROM的8位微控制器的閃存 |
| 文件頁數(shù)： | 40/88頁 |
| 文件大?。?/td> | 1495K |
| 代理商： | 35007B |
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PIC16F84A
DS35007B-page 38
2000 Microchip Technology Inc.
BTFSC
Bit Test, Skip if Clear
Syntax:
Operands:
[label BTFSC f,b
0
≤
f
≤
127
0
≤
b
≤
7
skip if (f<b>) = 0
None
If bit ’b’ in register ’f’ is ’1’, the next
instruction is executed.
If bit ’b’ in register ’f’ is ’0’, the next
instruction is discarded, and a
NOP
is executed instead, making this a
2T
CY
instruction.
Operation:
Status Affected:
Description:
CALL
Call Subroutine
Syntax:
Operands:
Operation:
[ label CALL k
0
≤
k
≤
2047
(PC)+ 1
→
TOS,
k
→
PC<10:0>,
(PCLATH<4:3>)
→
PC<12:11>
None
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven-bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH.
CALL
is
a two-cycle instruction.
Status Affected:
Description:
CLRF
Clear f
Syntax:
Operands:
Operation:
[label CLRF f
0
≤
f
≤
127
00h
→
(f)
1
→
Z
Z
The contents of register ’f’ are
cleared and the Z bit is set.
Status Affected:
Description:
CLRW
Clear W
Syntax:
Operands:
Operation:
[ label CLRW
None
00h
→
(W)
1
→
Z
Z
W register is cleared. Zero bit (Z)
is set.
Status Affected:
Description:
CLRWDT
Clear Watchdog Timer
Syntax:
Operands:
Operation:
[ label CLRWDT
None
00h
→
WDT
0
→
WDT prescaler,
1
→
TO
1
→
PD
TO, PD
CLRWDT
instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits
TO and PD are set.
Status Affected:
Description:
COMF
Complement f
Syntax:
Operands:
[ label COMF f,d
0
≤
f
≤
127
d
∈
[0,1]
(f)
→
(destination)
Z
The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W. If ’d’ is 1, the
result is stored back in register ’f’.
Operation:
Status Affected:
Description:
DECF
Decrement f
Syntax:
Operands:
[label DECF f,d
0
≤
f
≤
127
d
∈
[0,1]
(f) - 1
→
(destination)
Z
Decrement register ’f’. If ’d’ is 0,
the result is stored in the W regis-
ter. If ’d’ is 1, the result is stored
back in register ’f’.
Operation:
Status Affected:
Description:
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