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參數(shù)資料
| 型號： | 35007B |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 18-pin Enhanced FLASH/EEPROM 8-bit Microcontroller |
| 中文描述： | 18針/ EEPROM的8位微控制器的閃存 |
| 文件頁數(shù)： | 31/88頁 |
| 文件大小： | 1495K |
| 代理商： | 35007B |
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2001 Microchip Technology Inc.
DS35007B-page 29
PIC16F84A
6.8
Interrupts
The PIC16F84A has 4 sources of interrupt:
External interrupt RB0/INT pin
TMR0 overflow interrupt
PORTB change interrupts (pins RB7:RB4)
Data EEPROM write complete interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also contains
the individual and global interrupt enable bits.
The global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. Bit GIE is cleared on RESET.
The “return from interrupt” instruction,
RETFIE
, exits
interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. For external interrupt events, such as the
RB0/INT pin or PORTB change interrupt, the interrupt
latency will be three to four instruction cycles. The
exact latency depends when the interrupt event occurs.
The latency is the same for both one and two cycle
instructions. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid infinite interrupt requests.
FIGURE 6-10:
INTERRUPT LOGIC
6.8.1
INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION_REG<6>) is set,
or falling if INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing control bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software via the Interrupt Service
Routine before re-enabling this interrupt. The INT
interrupt can wake the processor from SLEEP
(Section 6.11) only if the INTE bit was set prior to going
into SLEEP. The status of the GIE bit decides whether
the processor branches to the interrupt vector
following wake-up.
6.8.2
TMR0 INTERRUPT
An overflow (FFh
→
00h) in TMR0 will set flag bit T0IF
(INTCON<2>). The interrupt can be enabled/disabled
by setting/clearing enable bit T0IE (INTCON<5>)
(Section 5.0).
6.8.3
PORTB INTERRUPT
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<3>)
(Section 4.2).
6.8.4
DATA EEPROM INTERRUPT
At the completion of a data EEPROM write cycle, flag
bit EEIF (EECON1<4>) will be set. The interrupt can be
enabled/disabled by setting/clearing enable bit EEIE
(INTCON<6>) (Section 3.0).
Note:
Individual interrupt flag bits are set
regardless
of
the
corresponding mask bit or the GIE bit.
status
of
their
RBIF
RBIE
T0IF
T0IE
INTF
INTE
GIE
EEIE
Wake-up
(If in SLEEP mode)
Interrupt to CPU
EEIF
Note:
For a change on the I/O pin to be
recognized, the pulse width must be at
least T
CY
wide.
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