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參數資料
| 型號： | 3D3215Z-6 |
| 元件分類： | 復位半導體 |
| 英文描述： | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 中文描述： | 延遲線 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 32K |
| 代理商： | 3D3215Z-6 |
3D3215
Doc #01014
12/3/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
MONOLITHIC 5-TAP 3.3V
FIXED DELAY LINE
(SERIES 3D3215)
FEATURES
PACKAGES
All-silicon, low-power 3.3V CMOS technology
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Delay range:
1.5ns through 300ns
Total delay tolerance:
2% or 0.5ns (3.3V, 25C)
Temperature stability:
±
1% typical (0C-70C)
Vdd stability:
±
1% typical (3.0V-3.6V)
Static Idd:
1.3ma typical
Minimum input pulse width:
25% of total delay
FUNCTIONAL DESCRIPTION
The 3D3215 5-Tap Delay Line product family consists of fixed-delay
3.3V CMOS integrated circuits. Each package contains a single delay
line, tapped and buffered at 5 points spaced uniformly in time. Tap-to-
tap (incremental) delay values can range from 1.5ns through 60ns. The
input is reproduced at the outputs without inversion, shifted in time as
per the user-specified dash number. The 3D3215 is 3.3V CMOS-
compatible and features both rising- and falling-edge accuracy.
The all-CMOS 3D3215 integrated circuit has been designed as a
reliable, economic alternative to hybrid fixed delay lines. It is offered in a
standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
DASH #
3D3215Z-xx
3D3215M-xx
-1.5
-2
-2.5
-3
-4
-5
-6
-8
-10
-12
-15
-20
-25
-30
-40
-50
-60
DELAY SPECIFICATIONS
TOTAL
DELAY (ns)
6.0
±
0.5*
8.0
±
0.5*
10.0
±
0.5*
12.0
±
0.5*
16.0
±
0.5*
20.0
±
0.5*
24.0
±
0.5*
40.0
±
0.8
50.0
±
1.0
60.0
±
1.2
75.0
±
1.5
100
±
2.0
125
±
2.5
150
±
3.0
200
±
4.0
250
±
5.0
300
±
6.0
INPUT RESTRICTIONS
RECOMMENDED
Max Freq
23.8 MHz
20.8 MHz
18.5 MHz
16.7 MHz
13.9 MHz
11.9 MHz
10.4 MHz
8.33 MHz
6.67 MHz
5.56 MHz
4.42 MHz
3.33 MHz
2.66 MHz
2.22 MHz
1.67 MHz
1.33 MHz
1.11 MHz
ABSOLUTE
TAP-TAP
DELAY (ns)
1.5
±
0.7
2.0
±
0.8
2.5
±
1.0
3.0
±
1.3
4.0
±
1.3
5.0
±
1.4
6.0
±
1.4
8.0
±
1.4
10.0
±
1.5
12.0
±
1.5
15.0
±
1.5
20.0
±
2.0
25.0
±
2.5
30.0
±
3.0
40.0
±
4.0
50.0
±
5.0
60.0
±
6.0
Min P.W.
21.0 ns
24.0 ns
27.0 ns
30.0 ns
36.0 ns
42.0 ns
48.0 ns
60.0 ns
75.0 ns
90.0 ns
113 ns
150 ns
188 ns
225 ns
300 ns
375 ns
450 ns
Max Freq
83.3 MHz
83.3 MHz
66.7 MHz
55.6 MHz
50.0 MHz
40.0 MHz
55.6 MHz
41.7 MHz
40.0 MHz
33.3 MHz
26.7 MHz
20.0 MHz
16.0 MHz
13.3 MHz
10.0 MHz
8.0 MHz
6.7 MHz
Min P.W.
6.00 ns
6.00 ns
7.50 ns
9.00 ns
10.00 ns
12.50 ns
9.00 ns
12.00 ns
12.50 ns
15.00 ns
18.75 ns
25.00 ns
31.25 ns
37.50 ns
50.00 ns
62.50 ns
75.00 ns
* Total delay referenced to Tap1 output; Input-to-Tap1 = 7.5ns
±
1.5ns
NOTE: Any dash number between 1.5 and 60 not shown is also available as standard
2001 Data Delay Devices
data
delay
devices,
inc.
3
8
7
6
5
1
2
3
4
IN
O2
O4
GND
VDD
O1
O3
O5
3D3215M-xx
DIP (300 Mil)
1
2
3
4
8
7
6
5
IN
O2
O4
GND
VDD
O1
O3
O5
3D3215Z-xx
SOIC (150 Mil)
PIN DESCRIPTIONS
IN
O1
O2
O3
O4
O5
VDD
GND
N/C
Delay Line Input
Tap 1 Output (20%)
Tap 2 Output (40%)
Tap 3 Output (60%)
Tap 4 Output (80%)
Tap 5 Output (100%)
+3.3 Volts
Ground
No Connection
For mechanical dimensions, click
here
.
For package marking details, click
here
.
相關PDF資料 |
PDF描述 |
|---|---|
| 3D3215 | MONOLITHIC 5-TAP 3.3V FIXED DELAY LINE |
| 3D3215SERIES | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 3D3428 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D3428-0.25 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D3428-0.5 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 3D3215Z-60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| 3D3215Z-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| 3D3220 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D3220) |
| 3D3220-.75 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D3220) |
| 3D3220_06 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 10-TAP FIXED DELAY LINE |
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