PPC405EX – PowerPC 405EX Embedded Processor
12
AMCC Proprietary
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
Media Access Control Security (MACSec) features
– Cipher suite GCM-AES-128
– Header insertion and removal
– Integrity and confidentiality with MSDU
SGT L2 supported features:
– GCM-AES with 128-bit key.
– Integrity only and with confidentiality of MSDU
ICV generation and validation SGT L3 supported features
– AES-GCM, AES-GMAC with 128, 192 and 256 bit key.
IPsec/SSL security acceleration engine
DES, 3DES, AES, ARC-4, AES-GCM, and GMAC-AES encryption/decryption
MD-5, SHA-1, and SHA-256 hashing
Public key acceleration for RSA, DSA and Diffie-Hellman
Combined encryption-hash and hash-decryption with the AES-CCM algorithm.
True or pseudo random number generators
– Non-deterministic true random numbers
– Pseudo random numbers with lengths of 8B or 16B
– ANSI X9.17 Annex C compliant using a DES algorithm
Interrupt controller
– Fifteen programmable, maskable interrupts
– Initiate commands via an input interrupt
– Sixteen programmable interrupts indicating completion of certain operations
– All interrupts mapped to one level- or edge-sensitive programmable interrupt output
DMA controller
– Autonomous, 4-channel
– 1024-words (32 bits/word) per DMA transfer
– Scatter/gather capability with byte aligned addressing
– Byte reverse capability on SA and descriptors
UART
The Universal Asynchronous Receiver/Transmitter (UART) interface provides four configurations:
One 8-signal port
Two 4-signal ports.
Two 2-signal ports
One 4-signal port and one 2-signal port
The UART performs serial-to-parallel conversion on data received from a peripheral device or a modem, and
parallel-to-serial conversion on data received from the processor.
Features include:
Compatible with the16750
All six software modem control functions (CTS, RTS, DSR, DTR, RI, DCD) on UART0
Programmable auto flow (data flow controlled by RTS and CTS signals)
Characters can be 5, 6, 7, or 8 bits
Programmable start, stop, parity bit insertion
Sixty-four byte FIFOs for buffering Tx and Rx data
LIN sub-bus specification compliant - line break generation/detection and false start bit detection
Programmable internal/external loopback capabilities
Low Power and Sleep mode
Register conformance (after reset) to configuration of the NS16450 register set
Hold and shift registers (eliminate need for precise synchronization between processor and serial data in
character mode)
Complete status reporting
Full prioritized interrupt system controls