參數(shù)資料
型號: 405EX
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 405EX Embedded Processor
中文描述: 嵌入式處理器的PowerPC 405EX
文件頁數(shù): 58/67頁
文件大?。?/td> 457K
代理商: 405EX
PPC405EX – PowerPC 405EX Embedded Processor
Revision 1.09 - August 21, 2007
AMCC Proprietary
61
Preliminary Data Sheet
DDR SDRAM Read Operation
The Read of the incoming Data from the SDRAM is done on the rising and falling edges of the differential DQS
signal. The Data must be centered to these edges for correct operation.
The PPC405EX can delay with very fine granularity the DQS through register programming.
DDR SDRAM MemClkOut0 and Read Clock Delay
In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data
path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency.
The data is stored in the eight Flip Flops of the Stage 1, such that it can be transferred later within a 8x period.
Table 22. I/O Timing—DDR SDRAM TSK, TSA, and THA
Signal Name
TSK (ns)
TSA (ns)
THA (ns)
MinimumMaximumMinimum
Minimum
MemAddr00:14
0.20
+2.3
BA0:2
BankSel0:1
MemClkEn
CAS
RAS
WE
Table 23. I/O Timing—DDR SDRAM Write TimingTSD and THD
Notes:
1. TSD and THD are measured under worst case conditions.
2. Clock speed for the values in the table is 200MHz.
3. The time values in the table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25 ns).
4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.5 ns from the values in the table and add 1/4
of the cycle time for the lower clock frequency (for example, TSD 1.25 + 0.25TCYC).
Signal Names
Reference Signal
TSD (ns)
THD (ns)
MemData00:07, DM0
DQS0
0.84
1.15
MemData08:15, DM1
DQS1
0.84
1.15
MemData16:23, DM2
DQS2
0.84
1.15
MemData24:31, DM3
DQS3
0.84
1.15
ECC0:7, DM4
DQS4
0.84
1.15
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