參數(shù)資料
型號(hào): 405EZ
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 405EZ Embedded Processor
中文描述: 嵌入式處理器的PowerPC 405EZ
文件頁(yè)數(shù): 38/54頁(yè)
文件大?。?/td> 362K
代理商: 405EZ
PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
AMCC Proprietary
43
Preliminary Data Sheet
Table 9. Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Notes
Logic Supply Voltage
VDD
+1.425
+1.5
+1.575
V
I/O Supply Voltage (for non-EBC I/O)
OVDD1
+3.0
+3.3
+3.6
V
I/O Supply Voltage (for EBC I/O)
OVDD2
+3.0
+3.3
+3.6
(see Note 1)
V1
PLL Analog Supply Voltage
PLL_AVDD
+1.4
+1.5
+1.6
V
ADC Analog Supply Voltage
ADC_AVDD
+3.135
+3.3
+3.465
V
DAC Analog Supply Voltage
DAC_AVDD
+3.135
+3.3
+3.465
V
I/O Input Low (3.3V LVTTL)
VIL
0+0.8
V
I/O Input High (3.3V LVTTL)
VIH
+2.0
+3.6
V
I/O Output Low (3.3V LVTTL)
VOL
0+0.4
V
I/O Output High (3.3V LVTTL)
VOH
+2.4
+3.6
V
I/O High (USB, 5V tolerant)
VOH
+2.8
V
I/O Low (USB, 5V tolerant)
VOL
+0.3
V
I/O Input High (IIC)
VIH
0.7OVDD
OVDD + 0.3
V
I/O Input Low (IIC)
VIL
0.3
+0.3OVDD
V
I/O Output High (IIC)
VIH
V
I/O Output Low (IIC)
VOL
0+0.4
V
Input Leakage Current
(no pull-up or pull-down)
IIL1
00
μA
Input Leakage Current
(with internal pull-down)
IIL2
0200
μA
I/O Maximum Allowable Overshoot
(3.3V LVTTL)
VMAO
+3.9
V
I/O Maximum Allowable Undershoot
(3.3V LVTTL)
VMAU
0.6
V
Case Temperature
TC
40
+105
°C
Notes:
1. When using CRAM or PSRAM memory on the EBC interface, this voltage must be limited to a maximum of +3.3V. This is a limitation
imposed by the CRAM/PSRAM devices, not the PPC405EZ.
Table 10. Input Capacitance
Parameter
Symbol
Maximum
Unit
Notes
3.3V LVTTL I/O
CIN1
1.9
pF
USB 5V Tolerant I/O
CIN2
3.2
pF
IIC I/O
CIN3
5.8
pF
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