參數(shù)資料
型號: 405EZ
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 405EZ Embedded Processor
中文描述: 嵌入式處理器的PowerPC 405EZ
文件頁數(shù): 47/54頁
文件大小: 362K
代理商: 405EZ
PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
AMCC Proprietary
51
Preliminary Data Sheet
Initialization
The following describes the method by which initial chip settings are established when a system reset occurs.
Strapping
When the SysReset input is driven low (system reset), the state of certain I/O pins is read in order to enable default
initial conditions before PPC405EZ start-up. The actual instant of capture is the nearest system clock edge before
the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)
resistors to select the desired default conditions. The recommended pull-up is 3k
Ω to +3.3V, or 10kΩ to +5V. The
recommended pull-down is 1K
Ω to GND. These pins are only used for strap functions during reset. They are used
for other signals during normal operation. The following table lists the strapping pins along with their functions and
strapping options. The signal names assigned to the pins for normal operation appear below the pin number.
Table 17. Strapping Pin Assignments
Pin Strapping
Function
Option
F03
(GPIO114)
E03
(GPIO112)
D01
(GPIO111)
D02
(GPIO110)
Initialize from EBC
8 bits wide
0000
16 bits wide
0001
32 bits wide
0010
Initialize from NAND Flash
512 page, 3 addr cycle
0011
512 page, 4 addr cycle
0100
2K page, 4 addr cycle
0101
2K page, 5 addr cycle
0110
Initialize from SPI
Slow
0111
Fast
1000
Reserved
na
1001
Initialize from IIC
Note: If reading of initialization data from
the IIC interface fails, the PPC405EZ
defaults to strapping option 0010.
na
1010
1011
1100
1101
1110
1111
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