參數(shù)資料
型號(hào)： 4565B2
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909
封裝： PLASTIC, BGA-909
文件頁(yè)數(shù)： 18/61頁(yè)
文件大?。?/td> 1691K
代理商： 4565B2
Hardware Design Guide, Revision 2
4565B Ultramapper Full Transport Retiming Device
December 17, 2003
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Agere Systems Inc.
25
The transmit path is toward the high-speed fiber output, and the receive path is from the high-speed input. Low-speed
inputs, e.g., LINERXDATA, on the transmit path, are labeled receive. Low-speed outputs, e.g., LINETXDATA, on the
receive path, are labeled transmit.
The transmit path is toward the high-speed fiber output, and the receive path is from the high-speed input. Low-speed
inputs, e.g., LINERXDATA, on the transmit path, are labeled receive. Low-speed outputs, e.g., LINETXDATA, on the
receive path, are labeled transmit.
Table 2-13. NSMI/STS-1 Out
Pin
Symbol
Type
Name/Description
AP33, AL25,
AN28
NSMITXDATA[3:1]
O
NSMI Transmit Data. NSMI outputs or STS-1 Tx data outputs from
STS1LTs. NSMI output data from either the SPEMPR or M13/E13 block.
AN31, AP31,
AG23
NSMITXCLK[3:1]
O
NSMI Transmit Clock Output or STS-1 Tx Clock Outputs from
STS1LTs. Output clock at 51.84 MHz for the STS-1 rate clear-channel
application, or the DS3/E3 application (44.736/34.368 MHz).
AL27, AP32,
AP30
NSMITXSYNC[3:1]
O
Transmit System Frame Sync Output. Output transmit control frame sync
signal from M13/E13 or SPEMPR.
AM29,
AM28, AN29
TXDATAEN[3:1]
O
Transmit Data Enable for NSMI Mode. This is used for an 8-pin NSMI mode
transmit control frame sync. More information will be published in a separate
operational guide.
* The transmit path is toward the high-speed fiber output, and the receive path is from the high-speed input. Low-speed inputs, e.g., NSMIRXDATA, on
the transmit path, are labeled receive. Low-speed outputs, e.g., NSMITXDATA, on the receive path, are labeled transmit.
Table 2-14. Shared Low-Speed Line In
Pin
Symbol
Type
Name/Description
T1, W2, V9, AB3, AG1, AA8, AC6, AE6, AD8,
AC34, AB34, W30, V31, V32, U34, U30, T32,
P34, R27, M33, L34, M32, P30, K34, L32,
N27, M29, L31, L29, G28, F28, E29, G27,
A33, F25, A30, D25, H23, A26, D22, E21, A22,
C18, H17, A17, D15, H15, C12, C11, F12,
H10, F5, G6, H8, G5, H6, E6, A4, A5, F8, C6,
B6, F10, A6, C7, F11, D8, A7, E11, B8, A8, A9,
A11, H13, F13, E13, A13, F14, D13, E14, E15,
H16, D16, B17, D17, E18
LINERXDATA[86:1] I pd Line Receive Data [86:1]. Inputs to the internal
multirate crossconnect.
These signals are used for received single-rail
DS1/E1 line data input, sourced from an exter-
nal LIU. In this mode, these signals will be rout-
ed via the crossconnect to the VT mapper, the
M13 multiplexer, E13 multiplexer, or the receive
line inputs of the DS1/E1 framers.
These signals may also be used as input data
for DS2/E2 applications (see the System
Design Guide).
T2, U1, W4, AA4, Y8, AD4, AE4, AH2, AH3,
AC33, Y30, AA34, W31, W34, V30, U33, T33,
T27, N34, M34, P29, N31, L33, N30, M31,
N29, M30, M27, L30, F29, E30, H26, D30,
D29, A32, H24, A29, B28, F22, B24, D21,
H20, D19, B18, E17, A16, D14, H14, A12,
A10, F6, E5, H9, C1, F4, J9, F7, B4, G8, D6,
E7, F9, E8, D7, E10, E9, B7, H11, C8, D9,
H12, D10, E12, B11, D11, B12, D12, B13, C13,
A14, A15, B16, C16, E16, C17, A18
LINERXCLK[86:1] I/0 pd Line Receive Clock [86:1]. Configurable
inputs to the internal multirate crossconnect.
These inputs are used for asynchronous clocks
associated with the line receive data inputs
from external line interface units, or payload
termination functions.
In certain cases, these pins can be used as
outputs. These pins may be used for DS2/E2
clocks in DS2/E2 applications. More informa-
tion will be published in the System Design
Guide.
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