參數(shù)資料
型號: 4565B2
元件分類: 數(shù)字傳輸電路
英文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909
封裝: PLASTIC, BGA-909
文件頁數(shù): 42/61頁
文件大?。?/td> 1691K
代理商: 4565B2
Hardware Design Guide, Revision 2
4565B Ultramapper Full Transport Retiming Device
December 17, 2003
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Agere Systems Inc.
47
5.8 Retiming Clock/Sync Timing
Figure 5-18. Retiming Clock Timing
* VIH to VIH or VIL to VIL.
Note: This figure assumes TMXR84622 is programmed to sample the frame sync signal on rising edge of the bit clock.
Figure 5-19. Retiming Bus Timing
Table 5-16. CHIRXGCLK and CHITXGCLK Timing Specifications
Parameter
Description
Min
Typ
Max
Unit
t1
Rise Time
2
7
ns
t2
Width (8.192 MHz)*
48.84
73.24
ns
t2
Width (16.384 MHz)*
24.42
36.62
ns
t3
Fall Time
2
7
ns
t4
Period (8.192 MHz)
122.07
ns
t4
Period (16.384 MHz)
61.03
ns
Table 5-17. Retiming Interface Timing Specifications
Parameter
Description
Min
Max
Unit
t5
Frame Sync Setup Time to Active CHI Clock Edge
15
ns
t6
Frame Sync Hold Time from Active CHI Clock Edge
4
ns
W
9''
9,/
9,+
9,/
t3
t4
50%
W2
&+,RXG&/.
W5
W6
CHIRXGFS
CHITXGFS
&+,TXG&/.
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