參數(shù)資料
型號(hào)： 4565B2
元件分類： 數(shù)字傳輸電路
英文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909
封裝： PLASTIC, BGA-909
文件頁(yè)數(shù)： 51/61頁(yè)
文件大?。?/td> 1691K
代理商： 4565B2
Hardware Design Guide, Revision 2
4565B Ultramapper Full Transport Retiming Device
December 17, 2003
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Agere Systems Inc.
55
7.3 Asynchronous Write Mode
The asynchronous microprocessor interface mode is selected when MPMODE (pin F6) = 0. Interface timing for the asyn-
chronous mode write cycle is given in Figure 7-3 and in Table 7-3, and for the read cycle in Figure 7-4 and in Table 7-4.
Although this is an asynchronous interface, an MPCLK is still required. This clock can be different (asynchronous) from the
MPU clock. Internal to the chip, RWN, ADSN, and DSN will be sampled by MPCLK.
For the asynchronous microprocessor mode of operation, it is recommended that the MPCLK applied to this device does
not exceed 50 MHz when the clock applied to the MPCLK pin is asynchronous to the microprocessor’s clock. For the case
where the microprocessor’s clock and the clock applied to this device’s MPCLK pin are synchronous, the maximum
MPCLK rate is 66 MHz.
Notes:
ADDR [20:0]
Address is asynchronously passed from the host bus to the internal bus. The address will be available throughout the entire cycle. ADDR
must be held constant while ADSN and DSN are valid (low).
CSN (Input)
Chip select is an active-low signal. CSN must be held low (active) until ADSN and DSN are deasserted.
ADSN (Input) Address strobe is active-low. ADSN must be stable for the entire period. ADSN and CSN may be connected and driven from the same
source.
DSN (Input)
Data strobe is active-low.
DATA [15:0]
Write data is asynchronously passed from the host bus to the internal bus. Data will be available throughout the entire cycle. DATA must
be held constant while DSN is valid (low).
RWN (Input)
The read/write signal should be high for a read cycle and low for a write cycle. It should always be held high, except during a write cycle.
RWN must be held low (write) until DSN is deasserted (high).
DTN (Output) Data transfer acknowledge (active-low). DTN is driven out of 3-state to inactive-high on the assertion of CSN. When the internal transac-
tion is complete, DTN goes active-low. DTN is then driven high again when either ADSN or DSN is deasserted. DTN will become 3-stated
when CSN is high. DTN fall is variable, depending on the block selected for access and in some cases the state of the SONET frame. This
interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. In lab measurements, it has never exceeded 1000 ns.
Figure 7-3. Microprocessor Interface Asynchronous Write Cycle—MPMODE = 0
ADDR[20:0]
CSN
ADSN
DSN
RWN
DATA[15:0]
DTN
(INPUT)
tAVADSF
tDVDSF
tCSFDTR
tDSFDTF
tADSRDTR
tCSRDT3
tDSRDI
tDSRRWR
tDSNRAI
tADSRAI
tAICSR
tRWFDSF
tAVDSF
HIGH Z
tCSFDSF
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