參數(shù)資料
型號(hào): 514JACXXXXXXAAG
廠商: SILICON LABORATORIES
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 125 MHz, OTHER CLOCK GENERATOR, PDSO6
封裝: 5 X 7 MM, ROHS COMPILANT PACKAGE-6
文件頁(yè)數(shù): 17/32頁(yè)
文件大?。?/td> 267K
代理商: 514JACXXXXXXAAG
Si514
24
Preliminary Rev. 0.9
5. Pin Descriptions
5.1. Dual CMOS (1:2 Fanout Buffer)
Dual CMOS output format ordering options support either complementary or in-phase output signals. This feature
enables replacement of multiple XOs with a single Si514 device.
Figure 7. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs
Table 12. Si514 Pin Descriptions
Pin
Name
Function
1
SDA
I2C Serial Data.
2
SCL
I2C Serial Clock.
3
GND
Electrical and Case Ground.
4
CLK+
Clock Output.
5
CLK-
Complementary clock output (LVPECL, LVDS, HCSL, and
Complementary dual CMOS formats).
Clock output for in-phase dual CMOS format.
No connect (N/C) for single-ended CMOS format.
6
VDD
Power Supply Voltage.
1
2
3
6
5
4
GND
SCL
VDD
CLK+
CLK–
SDA
~
Complementary
Outputs
In-Phase
Outputs
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