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參數(shù)資料
| 型號(hào)： | 534AB000359DG |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK XO QUAD FREQUENCY 8SMD |
| 應(yīng)用說明： | Frequency Margining using the SI534 |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 系列： | Si534 |
| 類型： | 振蕩器 - 晶體 |
| 頻率： | 167.33MHz，173.37MHz，193.77MHz，194.89MHz |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 電流 - 電源： | 111mA |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SMD，無引線 |
| 包裝： | 托盤 |
| 供應(yīng)商設(shè)備封裝： | 8-SMD |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | Q4733547A |
Si534
Rev. 1.3
11
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1
Updated Table 1, “Recommended Operating
Device maintains stable operation over –40 to +85 C
operating temperature range.
Supply current specifications updated for revision D.
Updated Table 2, “CLK± Output Frequency
Added specification for ±20 ppm lifetime stability
(±7 ppm temperature stability) XO.
Updated Table 3, “CLK± Output Levels and
Updated LVDS differential peak-peak swing
specifications.
Revised period jitter specifications.
page 5 to reflect the soldering temperature time at
260 C is 20–40 sec per JEDEC J-STD-020C.
Changed ordering instructions to revision D.
Revision 1.1 to Revision 1.2
Updated 2.5 V/3.3 V and 1.8 V CML output level
specifications for Table 3 on page 3.
Added footnotes clarifying max offset frequency test
conditions for Table 4 on page 4.
Removed the words "Differential Modes:
LVPECL/LVDS/CML" in the footnote referring to
AN256 in Table 4 on page 4.
Added CMOS phase jitter specs to Table 4 on
Updated ESD HBM sensitivity rating in Table 9 on
Updated Table 7 on page 5 to include the "Moisture
Sensitivity Level" and "Contact Pads" rows.
Revised Figure 2 on page 8 to reflect current
package outline diagram.
Updated Figure 3 and Table 12 on page 9 to reflect
specific marking information. Previously, Figure 3
was generic.
Revision 1.2 to Revision 1.3
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