Phase Jitter (RMS)
參數(shù)資料
型號: 534AB000359DG
廠商: Silicon Laboratories Inc
文件頁數(shù): 7/12頁
文件大小: 0K
描述: IC CLK XO QUAD FREQUENCY 8SMD
應用說明: Frequency Margining using the SI534
標準包裝: 50
系列: Si534
類型: 振蕩器 - 晶體
頻率: 167.33MHz,173.37MHz,193.77MHz,194.89MHz
電源電壓: 1.71 V ~ 3.63 V
電流 - 電源: 111mA
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SMD,無引線
包裝: 托盤
供應商設備封裝: 8-SMD
安裝類型: 表面貼裝
其它名稱: Q4733547A
Si534
4
Rev. 1.3
Table 4. CLK± Output Phase Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Phase Jitter (RMS)1
for FOUT > 500 MHz
J
12 kHz to 20 MHz (OC-48)
0.25
0.40
ps
50 kHz to 80 MHz (OC-192)
0.26
0.37
ps
Phase Jitter (RMS)1
for FOUT of 125 to 500 MHz
J
12 kHz to 20 MHz (OC-48)
0.36
0.50
ps
50 kHz to 80 MHz (OC-192)2
0.34
0.42
ps
Phase Jitter (RMS)
for FOUT of 10 to 160 MHz
CMOS Output Only
J
12 kHz to 20 MHz (OC-48)2
—0.62
ps
50 kHz to 20 MHz2
—0.61
ps
Notes:
1. Refer to AN256 for further information.
2. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
2 MHz for 10 MHz < FOUT <50 MHz.
Table 5. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Period Jitter*
JPER
RMS
2
ps
Peak-to-Peak
14
ps
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 6. CLK± Output Phase Noise (Typical)
Offset Frequency (f)
120.00 MHz
LVDS
156.25 MHz
LVPECL
622.08 MHz
LVPECL
Units
100 Hz
1kHz
10 kHz
100 kHz
1MHz
10 MHz
100 MHz
–112
–122
–132
–137
–144
–150
n/a
–105
–122
–128
–135
–144
–147
n/a
–97
–107
–116
–121
–134
–146
–148
dBc/Hz
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